Hypervisor need information about the current state of LVT registers
for device emulation and NMI. So, forward reads and write of these
registers to the hypervisor for Secure AVIC enabled guests.
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
---
Changes since v6:
- No change.
arch/x86/kernel/apic/x2apic_savic.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index 583b57636f21..0fecc295874e 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -69,6 +69,11 @@ static u32 savic_read(u32 reg)
case APIC_TMICT:
case APIC_TMCCT:
case APIC_TDCR:
+ case APIC_LVTTHMR:
+ case APIC_LVTPC:
+ case APIC_LVT0:
+ case APIC_LVT1:
+ case APIC_LVTERR:
return savic_ghcb_msr_read(reg);
case APIC_ID:
case APIC_LVR:
@@ -78,11 +83,6 @@ static u32 savic_read(u32 reg)
case APIC_LDR:
case APIC_SPIV:
case APIC_ESR:
- case APIC_LVTTHMR:
- case APIC_LVTPC:
- case APIC_LVT0:
- case APIC_LVT1:
- case APIC_LVTERR:
case APIC_EFEAT:
case APIC_ECTRL:
case APIC_SEOI:
@@ -204,18 +204,18 @@ static void savic_write(u32 reg, u32 data)
case APIC_LVTT:
case APIC_TMICT:
case APIC_TDCR:
- savic_ghcb_msr_write(reg, data);
- break;
case APIC_LVT0:
case APIC_LVT1:
+ case APIC_LVTTHMR:
+ case APIC_LVTPC:
+ case APIC_LVTERR:
+ savic_ghcb_msr_write(reg, data);
+ break;
case APIC_TASKPRI:
case APIC_EOI:
case APIC_SPIV:
case SAVIC_NMI_REQ:
case APIC_ESR:
- case APIC_LVTTHMR:
- case APIC_LVTPC:
- case APIC_LVTERR:
case APIC_ECTRL:
case APIC_SEOI:
case APIC_IER:
--
2.34.1