Flatten usb controller node and update to using latest bindings
and flattened driver approach.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 60 +++++++++++++++++++++++--
 1 file changed, 57 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index 0580408485eb..bd6cb895b65b 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -500,19 +500,73 @@ &ufs_mem_phy {
 	vdda-pll-supply = <&vreg_l6b_1p2>;
 };
 
+/delete-node/ &usb_1_dwc3;
+
 &usb_1 {
-	status = "okay";
-};
+	compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3";
+	reg = <0x0 0x0a600000 0x0 0x10000>;
+
+	/delete-property/ ranges;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+			      <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
+			      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+			      <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
+	interrupt-names = "dwc_usb3",
+			  "pwr_event",
+			  "hs_phy_irq",
+			  "dp_hs_phy_irq",
+			  "dm_hs_phy_irq",
+			  "ss_phy_irq";
+
+	iommus = <&apps_smmu 0x0 0x0>;
+
+	maximum-speed = "super-speed-plus";
+
+	phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+	phy-names = "usb2-phy", "usb3-phy";
+
+	snps,dis_u2_susphy_quirk;
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
 
-&usb_1_dwc3 {
 	dr_mode = "otg";
 	usb-role-switch;
+	wakeup-source;
+
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			usb_1_dwc3_hs: endpoint {
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			usb_1_dwc3_ss: endpoint {
+			};
+		};
+	};
 };
 
 &usb_1_dwc3_hs {
 	remote-endpoint = <&pmic_glink_hs_in>;
 };
 
+&usb_1_dwc3_ss {
+	remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+};
+
 &usb_1_hsphy {
 	status = "okay";
 
-- 
2.34.1

On Tue, Jun 10, 2025 at 02:48:05PM +0530, Krishna Kurapati wrote:
> Flatten usb controller node and update to using latest bindings
> and flattened driver approach.
> 
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 60 +++++++++++++++++++++++--
>  1 file changed, 57 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
> index 0580408485eb..bd6cb895b65b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
> @@ -500,19 +500,73 @@ &ufs_mem_phy {
>  	vdda-pll-supply = <&vreg_l6b_1p2>;
>  };
>  
> +/delete-node/ &usb_1_dwc3;
> +
>  &usb_1 {
> -	status = "okay";
> -};
> +	compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3";
> +	reg = <0x0 0x0a600000 0x0 0x10000>;

All these properties should go to the sm8450.dtsi rather than rewriting
them in the board file.

> +
> +	/delete-property/ ranges;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> +			      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> +			      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> +			      <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
> +			      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> +			      <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
> +	interrupt-names = "dwc_usb3",
> +			  "pwr_event",
> +			  "hs_phy_irq",
> +			  "dp_hs_phy_irq",
> +			  "dm_hs_phy_irq",
> +			  "ss_phy_irq";
> +
> +	iommus = <&apps_smmu 0x0 0x0>;
> +
> +	maximum-speed = "super-speed-plus";
> +
> +	phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> +	phy-names = "usb2-phy", "usb3-phy";
> +
> +	snps,dis_u2_susphy_quirk;
> +	snps,dis_enblslpm_quirk;
> +	snps,dis-u1-entry-quirk;
> +	snps,dis-u2-entry-quirk;
>  
> -&usb_1_dwc3 {
>  	dr_mode = "otg";
>  	usb-role-switch;
> +	wakeup-source;
> +
> +	status = "okay";
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +			usb_1_dwc3_hs: endpoint {
> +			};
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +			usb_1_dwc3_ss: endpoint {
> +			};
> +		};
> +	};
>  };
>  
>  &usb_1_dwc3_hs {
>  	remote-endpoint = <&pmic_glink_hs_in>;
>  };
>  
> +&usb_1_dwc3_ss {
> +	remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;

This is a part of the SoC routing, so it should go to sm8450.dtsi too.

> +};
> +
>  &usb_1_hsphy {
>  	status = "okay";
>  
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry