v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().
Notable changes in v6:
Correct fg_alpha shift on new DPU, pointed out by Abel Vesas.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v6:
1. Checkpatch: CHECK: Prefer kernel type 'u32' over 'uint32_t'
2. Fix for fg_alpha shift (Abel Vesa).
Changes in v4:
1. Lowercase hex, use spaces for define indentation
2. _dpu_crtc_setup_blend_cfg(): pass mdss_ver instead of ctl
Changes in v3:
1. New patch, split from previous big DPU v12.0.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 23 ++++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++++--
2 files changed, 97 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 92f6c39eee3dc090bd957239e58793e5b0437548..5e986640c8ce5b49d0ce2f91cc47f677a2e3f061 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -320,14 +320,22 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, const struct msm_format *format)
+ struct dpu_plane_state *pstate,
+ const struct msm_format *format,
+ const struct dpu_mdss_version *mdss_ver)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
u32 blend_op;
- u32 fg_alpha, bg_alpha;
+ u32 fg_alpha, bg_alpha, max_alpha;
- fg_alpha = pstate->base.alpha >> 8;
- bg_alpha = 0xff - fg_alpha;
+ if (mdss_ver->core_major_ver < 12) {
+ max_alpha = 0xff;
+ fg_alpha = pstate->base.alpha >> 8;
+ } else {
+ max_alpha = 0x3ff;
+ fg_alpha = pstate->base.alpha >> 6;
+ }
+ bg_alpha = max_alpha - fg_alpha;
/* default to opaque blending */
if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
@@ -337,7 +345,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
DPU_BLEND_BG_ALPHA_FG_PIXEL;
- if (fg_alpha != 0xff) {
+ if (fg_alpha != max_alpha) {
bg_alpha = fg_alpha;
blend_op |= DPU_BLEND_BG_MOD_ALPHA |
DPU_BLEND_BG_INV_MOD_ALPHA;
@@ -348,7 +356,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
/* coverage blending */
blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
DPU_BLEND_BG_ALPHA_FG_PIXEL;
- if (fg_alpha != 0xff) {
+ if (fg_alpha != max_alpha) {
bg_alpha = fg_alpha;
blend_op |= DPU_BLEND_FG_MOD_ALPHA |
DPU_BLEND_FG_INV_MOD_ALPHA |
@@ -481,7 +489,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
- _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
+ _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format,
+ ctl->mdss_ver);
if (bg_alpha_enable && !format->alpha_enable)
mixer[lm_idx].mixer_op_mode = 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..f220a68e138cb9e7c88194e53e47391de7ed04f7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -19,12 +19,20 @@
/* These register are offset to mixer base + stage base */
#define LM_BLEND0_OP 0x00
+
+/* <v12 DPU with offset to mixer base + stage base */
#define LM_BLEND0_CONST_ALPHA 0x04
#define LM_FG_COLOR_FILL_COLOR_0 0x08
#define LM_FG_COLOR_FILL_COLOR_1 0x0C
#define LM_FG_COLOR_FILL_SIZE 0x10
#define LM_FG_COLOR_FILL_XY 0x14
+/* >= v12 DPU */
+#define LM_BORDER_COLOR_0_V12 0x1c
+#define LM_BORDER_COLOR_1_V12 0x20
+
+/* >= v12 DPU with offset to mixer base + stage base */
+#define LM_BLEND0_CONST_ALPHA_V12 0x08
#define LM_BLEND0_FG_ALPHA 0x04
#define LM_BLEND0_BG_ALPHA 0x08
@@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
}
}
+static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx,
+ struct dpu_mdss_color *color,
+ u8 border_en)
+{
+ struct dpu_hw_blk_reg_map *c = &ctx->hw;
+
+ if (border_en) {
+ DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,
+ (color->color_0 & 0x3ff) |
+ ((color->color_1 & 0x3ff) << 16));
+ DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,
+ (color->color_2 & 0x3ff) |
+ ((color->color_3 & 0x3ff) << 16));
+ }
+}
+
static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
{
dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
@@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
}
+static void
+dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
+ u32 stage, u32 fg_alpha,
+ u32 bg_alpha, u32 blend_op)
+{
+ struct dpu_hw_blk_reg_map *c = &ctx->hw;
+ int stage_off;
+ u32 const_alpha;
+
+ if (stage == DPU_STAGE_BASE)
+ return;
+
+ stage_off = _stage_offset(ctx, stage);
+ if (WARN_ON(stage_off < 0))
+ return;
+
+ const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
+ DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
+ DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
+}
+
static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
{
@@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
}
+static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx,
+ uint32_t mixer_op_mode)
+{
+ struct dpu_hw_blk_reg_map *c = &ctx->hw;
+ int op_mode, stages, stage_off, i;
+
+ stages = ctx->cap->sblk->maxblendstages;
+ if (stages <= 0)
+ return;
+
+ for (i = DPU_STAGE_0; i <= stages; i++) {
+ stage_off = _stage_offset(ctx, i);
+ if (WARN_ON(stage_off < 0))
+ return;
+
+ /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */
+ op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);
+ if (mixer_op_mode & BIT(i))
+ op_mode |= BIT(30);
+ else
+ op_mode &= ~BIT(30);
+
+ DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);
+ }
+}
+
/**
* dpu_hw_lm_init() - Initializes the mixer hw driver object.
* should be called once before accessing every mixer.
@@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
c->idx = cfg->id;
c->cap = cfg;
c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
- if (mdss_ver->core_major_ver >= 4)
+ if (mdss_ver->core_major_ver >= 12)
+ c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12;
+ else if (mdss_ver->core_major_ver >= 4)
c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
else
c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
- c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
- c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
+ if (mdss_ver->core_major_ver < 12) {
+ c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
+ c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
+ } else {
+ c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12;
+ c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12;
+ }
c->ops.setup_misr = dpu_hw_lm_setup_misr;
c->ops.collect_misr = dpu_hw_lm_collect_misr;
--
2.45.2On 10/06/2025 16:05, Krzysztof Kozlowski wrote:
> v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
> differences and new implementations of setup_alpha_out(),
> setup_border_color() and setup_blend_config().
>
> Notable changes in v6:
> Correct fg_alpha shift on new DPU, pointed out by Abel Vesas.
-------------------------------------------------------- Vesa
Not sure this should be in the commit message.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Changes in v6:
> 1. Checkpatch: CHECK: Prefer kernel type 'u32' over 'uint32_t'
> 2. Fix for fg_alpha shift (Abel Vesa).
>
> Changes in v4:
> 1. Lowercase hex, use spaces for define indentation
> 2. _dpu_crtc_setup_blend_cfg(): pass mdss_ver instead of ctl
>
> Changes in v3:
> 1. New patch, split from previous big DPU v12.0.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 23 ++++++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++++--
> 2 files changed, 97 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 92f6c39eee3dc090bd957239e58793e5b0437548..5e986640c8ce5b49d0ce2f91cc47f677a2e3f061 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -320,14 +320,22 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
> }
>
> static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> - struct dpu_plane_state *pstate, const struct msm_format *format)
> + struct dpu_plane_state *pstate,
> + const struct msm_format *format,
> + const struct dpu_mdss_version *mdss_ver)
> {
> struct dpu_hw_mixer *lm = mixer->hw_lm;
> u32 blend_op;
> - u32 fg_alpha, bg_alpha;
> + u32 fg_alpha, bg_alpha, max_alpha;
>
> - fg_alpha = pstate->base.alpha >> 8;
> - bg_alpha = 0xff - fg_alpha;
> + if (mdss_ver->core_major_ver < 12) {
> + max_alpha = 0xff;
> + fg_alpha = pstate->base.alpha >> 8;
> + } else {
> + max_alpha = 0x3ff;
> + fg_alpha = pstate->base.alpha >> 6;
> + }
> + bg_alpha = max_alpha - fg_alpha;
>
> /* default to opaque blending */
> if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> @@ -337,7 +345,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
> blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
> DPU_BLEND_BG_ALPHA_FG_PIXEL;
> - if (fg_alpha != 0xff) {
> + if (fg_alpha != max_alpha) {
> bg_alpha = fg_alpha;
> blend_op |= DPU_BLEND_BG_MOD_ALPHA |
> DPU_BLEND_BG_INV_MOD_ALPHA;
> @@ -348,7 +356,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> /* coverage blending */
> blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
> DPU_BLEND_BG_ALPHA_FG_PIXEL;
> - if (fg_alpha != 0xff) {
> + if (fg_alpha != max_alpha) {
> bg_alpha = fg_alpha;
> blend_op |= DPU_BLEND_FG_MOD_ALPHA |
> DPU_BLEND_FG_INV_MOD_ALPHA |
> @@ -481,7 +489,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>
> /* blend config update */
> for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
> - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
> + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format,
> + ctl->mdss_ver);
>
> if (bg_alpha_enable && !format->alpha_enable)
> mixer[lm_idx].mixer_op_mode = 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..f220a68e138cb9e7c88194e53e47391de7ed04f7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> @@ -19,12 +19,20 @@
>
> /* These register are offset to mixer base + stage base */
> #define LM_BLEND0_OP 0x00
> +
> +/* <v12 DPU with offset to mixer base + stage base */
> #define LM_BLEND0_CONST_ALPHA 0x04
> #define LM_FG_COLOR_FILL_COLOR_0 0x08
> #define LM_FG_COLOR_FILL_COLOR_1 0x0C
> #define LM_FG_COLOR_FILL_SIZE 0x10
> #define LM_FG_COLOR_FILL_XY 0x14
>
> +/* >= v12 DPU */
> +#define LM_BORDER_COLOR_0_V12 0x1c
> +#define LM_BORDER_COLOR_1_V12 0x20
> +
> +/* >= v12 DPU with offset to mixer base + stage base */
> +#define LM_BLEND0_CONST_ALPHA_V12 0x08
> #define LM_BLEND0_FG_ALPHA 0x04
> #define LM_BLEND0_BG_ALPHA 0x08
>
> @@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
> }
> }
>
> +static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx,
> + struct dpu_mdss_color *color,
> + u8 border_en)
> +{
> + struct dpu_hw_blk_reg_map *c = &ctx->hw;
> +
> + if (border_en) {
> + DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,
> + (color->color_0 & 0x3ff) |
> + ((color->color_1 & 0x3ff) << 16));
> + DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,
> + (color->color_2 & 0x3ff) |
> + ((color->color_3 & 0x3ff) << 16));
> + }
> +}
> +
> static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
> {
> dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
> @@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx
> DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
> }
>
> +static void
> +dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
> + u32 stage, u32 fg_alpha,
> + u32 bg_alpha, u32 blend_op)
> +{
> + struct dpu_hw_blk_reg_map *c = &ctx->hw;
> + int stage_off;
> + u32 const_alpha;
> +
> + if (stage == DPU_STAGE_BASE)
> + return;
> +
> + stage_off = _stage_offset(ctx, stage);
> + if (WARN_ON(stage_off < 0))
> + return;
> +
> + const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
> + DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
> + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
> +}
> +
> static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
> u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
> {
> @@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
> DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
> }
>
> +static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx,
> + uint32_t mixer_op_mode)
> +{
> + struct dpu_hw_blk_reg_map *c = &ctx->hw;
> + int op_mode, stages, stage_off, i;
> +
> + stages = ctx->cap->sblk->maxblendstages;
> + if (stages <= 0)
> + return;
> +
> + for (i = DPU_STAGE_0; i <= stages; i++) {
> + stage_off = _stage_offset(ctx, i);
> + if (WARN_ON(stage_off < 0))
> + return;
> +
> + /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */
> + op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);
> + if (mixer_op_mode & BIT(i))
> + op_mode |= BIT(30);
> + else
> + op_mode &= ~BIT(30);
> +
> + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);
> + }
> +}
> +
> /**
> * dpu_hw_lm_init() - Initializes the mixer hw driver object.
> * should be called once before accessing every mixer.
> @@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
> c->idx = cfg->id;
> c->cap = cfg;
> c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
> - if (mdss_ver->core_major_ver >= 4)
> + if (mdss_ver->core_major_ver >= 12)
> + c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12;
> + else if (mdss_ver->core_major_ver >= 4)
> c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
> else
> c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
> - c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
> - c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
> + if (mdss_ver->core_major_ver < 12) {
> + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
> + c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
> + } else {
> + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12;
> + c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12;
> + }
> c->ops.setup_misr = dpu_hw_lm_setup_misr;
> c->ops.collect_misr = dpu_hw_lm_collect_misr;
>
>
On 10/06/2025 16:10, Neil Armstrong wrote: > On 10/06/2025 16:05, Krzysztof Kozlowski wrote: >> v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register >> differences and new implementations of setup_alpha_out(), >> setup_border_color() and setup_blend_config(). >> >> Notable changes in v6: >> Correct fg_alpha shift on new DPU, pointed out by Abel Vesas. > > -------------------------------------------------------- Vesa > > Not sure this should be in the commit message. DRM, at least multiple DRM-subsystems, adds full changelogs to the commit msg, so I think adding notable part is worth. Best regards, Krzysztof
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