.../bindings/net/altr,gmii-to-sgmii.yaml | 49 ++++++ .../bindings/net/altr,socfpga-stmmac.yaml | 162 ++++++++++++++++++ .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------ MAINTAINERS | 7 +- 4 files changed, 217 insertions(+), 58 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml create mode 100644 Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
Convert the bindings for socfpga-dwmac to yaml. Since the original
text contained descriptions for two separate nodes, two separate
yaml files were created.
Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v4:
- Change filename from socfpga,dwmac.yaml to altr,socfpga-stmmac.yaml.
- Updated compatible in select properties and main properties.
- Fixed clocks so stmmaceth clock is required.
- Added binding for altr,gmii-to-sgmii.
- Update MAINTAINERS.
v3:
- Add missing supported phy-modes.
v2:
- Add compatible to required.
- Add descriptions for clocks.
- Add clock-names.
- Clean up items: in altr,sysmgr-syscon.
- Change "additionalProperties: true" to "unevaluatedProperties: false".
- Add properties needed for "unevaluatedProperties: false".
- Fix indentation in examples.
- Drop gmac0: label in examples.
- Exclude support for Arria10 that is not validating.
---
.../bindings/net/altr,gmii-to-sgmii.yaml | 49 ++++++
.../bindings/net/altr,socfpga-stmmac.yaml | 162 ++++++++++++++++++
.../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------
MAINTAINERS | 7 +-
4 files changed, 217 insertions(+), 58 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml
create mode 100644 Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
diff --git a/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml
new file mode 100644
index 000000000000..c0f61af3bde4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2025 Altera Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera GMII to SGMII Converter
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@altera.com>
+
+description:
+ This binding describes the Altera GMII to SGMII converter.
+
+properties:
+ comptatible:
+ const: altr,gmii-to-sgmii-2.0
+
+ reg:
+ items:
+ - description: Registers for the emac splitter IP
+ - description: Registers for the GMII to SGMII converter.
+ - description: Registers for TSE control.
+
+ reg-names:
+ items:
+ - const: hps_emac_interface_splitter_avalon_slave
+ - const: gmii_to_sgmii_adapter_avalon_slave
+ - const: eth_tse_control_port
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ phy@ff000240 {
+ compatible = "altr,gmii-to-sgmii-2.0";
+ reg = <0xff000240 0x00000008>,
+ <0xff000200 0x00000040>,
+ <0xff000250 0x00000008>;
+ reg-names = "hps_emac_interface_splitter_avalon_slave",
+ "gmii_to_sgmii_adapter_avalon_slave",
+ "eth_tse_control_port";
+ };
diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
new file mode 100644
index 000000000000..ccbbdb870755
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA SoC DWMAC controller
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@altera.com>
+
+description:
+ This binding describes the Altera SOCFPGA SoC implementation of the
+ Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
+ of chips.
+ # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
+ # does not validate against net/snps,dwmac.yaml.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - altr,socfpga-stmmac
+ - altr,socfpga-stmmac-a10-s10
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: altr,socfpga-stmmac
+ - const: snps,dwmac-3.70a
+ - const: snps,dwmac
+ - items:
+ - const: altr,socfpga-stmmac-a10-s10
+ - const: snps,dwmac-3.74a
+ - const: snps,dwmac
+
+ clocks:
+ minItems: 1
+ items:
+ - description: GMAC main clock
+ - description:
+ PTP reference clock. This clock is used for programming the
+ Timestamp Addend Register. If not passed then the system
+ clock will be used and this is fine on some platforms.
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: stmmaceth
+ - const: ptp_ref
+
+ iommus:
+ maxItems: 1
+
+ phy-mode:
+ enum:
+ - gmii
+ - mii
+ - rgmii
+ - rgmii-id
+ - rgmii-rxid
+ - rgmii-txid
+ - sgmii
+ - 1000base-x
+
+ rxc-skew-ps:
+ description: Skew control of RXC pad
+
+ rxd0-skew-ps:
+ description: Skew control of RX data 0 pad
+
+ rxd1-skew-ps:
+ description: Skew control of RX data 1 pad
+
+ rxd2-skew-ps:
+ description: Skew control of RX data 2 pad
+
+ rxd3-skew-ps:
+ description: Skew control of RX data 3 pad
+
+ rxdv-skew-ps:
+ description: Skew control of RX CTL pad
+
+ txc-skew-ps:
+ description: Skew control of TXC pad
+
+ txen-skew-ps:
+ description: Skew control of TXC pad
+
+ altr,emac-splitter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the emac splitter soft IP node if DWMAC
+ controller is connected an emac splitter.
+
+ altr,f2h_ptp_ref_clk:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to Precision Time Protocol reference clock. This clock is
+ common to gmac instances and defaults to osc1.
+
+ altr,gmii-to-sgmii-converter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the gmii to sgmii converter soft IP.
+
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Should be the phandle to the system manager node that encompass
+ the glue register, the register offset, and the register shift.
+ On Cyclone5/Arria5, the register shift represents the PHY mode
+ bits, while on the Arria10/Stratix10/Agilex platforms, the
+ register shift represents bit for each emac to enable/disable
+ signals from the FPGA fabric to the EMAC modules.
+ items:
+ - items:
+ - description: phandle to the system manager node
+ - description: offset of the control register
+ - description: shift within the control register
+
+patternProperties:
+ "^mdio[0-9]$":
+ type: object
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - altr,sysmgr-syscon
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ethernet@ff700000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
+ "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+ reg = <0xff700000 0x2000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
+ clocks = <&emac_0_clk>;
+ clock-names = "stmmaceth";
+ phy-mode = "sgmii";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
deleted file mode 100644
index 612a8e8abc88..000000000000
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Altera SOCFPGA SoC DWMAC controller
-
-This is a variant of the dwmac/stmmac driver an inherits all descriptions
-present in Documentation/devicetree/bindings/net/stmmac.txt.
-
-The device node has additional properties:
-
-Required properties:
- - compatible : For Cyclone5/Arria5 SoCs it should contain
- "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
- "altr,socfpga-stmmac-a10-s10".
- Along with "snps,dwmac" and any applicable more detailed
- designware version numbers documented in stmmac.txt
- - altr,sysmgr-syscon : Should be the phandle to the system manager node that
- encompasses the glue register, the register offset, and the register shift.
- On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
- on the Arria10/Stratix10/Agilex platforms, the register shift represents
- bit for each emac to enable/disable signals from the FPGA fabric to the
- EMAC modules.
- - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
- for ptp ref clk. This affects all emacs as the clock is common.
-
-Optional properties:
-altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
- DWMAC controller is connected emac splitter.
-phy-mode: The phy mode the ethernet operates in
-altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
-
-This device node has additional phandle dependency, the sgmii converter:
-
-Required properties:
- - compatible : Should be altr,gmii-to-sgmii-2.0
- - reg-names : Should be "eth_tse_control_port"
-
-Example:
-
-gmii_to_sgmii_converter: phy@100000240 {
- compatible = "altr,gmii-to-sgmii-2.0";
- reg = <0x00000001 0x00000240 0x00000008>,
- <0x00000001 0x00000200 0x00000040>;
- reg-names = "eth_tse_control_port";
- clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
- clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
-};
-
-gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
- phy-mode = "sgmii";
- altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
-};
diff --git a/MAINTAINERS b/MAINTAINERS
index ee93363ec2cb..bc24a6186abd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3262,10 +3262,15 @@ M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained
F: drivers/clk/socfpga/
+ARM/SOCFPGA DWMAC GLUE LAYER BINDINGS
+M: Matthew Gerlach <matthew.gerlach@altera.com>
+S: Maintained
+F: Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml
+F: Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
+
ARM/SOCFPGA DWMAC GLUE LAYER
M: Maxime Chevallier <maxime.chevallier@bootlin.com>
S: Maintained
-F: Documentation/devicetree/bindings/net/socfpga-dwmac.txt
F: drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
ARM/SOCFPGA EDAC BINDINGS
--
2.35.3On Mon, Jun 09, 2025 at 09:37:25AM -0700, Matthew Gerlach wrote: > Convert the bindings for socfpga-dwmac to yaml. Since the original > text contained descriptions for two separate nodes, two separate > yaml files were created. > > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> > --- > v4: > - Change filename from socfpga,dwmac.yaml to altr,socfpga-stmmac.yaml. > - Updated compatible in select properties and main properties. > - Fixed clocks so stmmaceth clock is required. > - Added binding for altr,gmii-to-sgmii. > - Update MAINTAINERS. > > v3: > - Add missing supported phy-modes. > > v2: > - Add compatible to required. > - Add descriptions for clocks. > - Add clock-names. > - Clean up items: in altr,sysmgr-syscon. > - Change "additionalProperties: true" to "unevaluatedProperties: false". > - Add properties needed for "unevaluatedProperties: false". > - Fix indentation in examples. > - Drop gmac0: label in examples. > - Exclude support for Arria10 that is not validating. > --- > .../bindings/net/altr,gmii-to-sgmii.yaml | 49 ++++++ > .../bindings/net/altr,socfpga-stmmac.yaml | 162 ++++++++++++++++++ > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------ > MAINTAINERS | 7 +- > 4 files changed, 217 insertions(+), 58 deletions(-) > create mode 100644 Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml altr,gmii-to-sgmii-2.0.yaml > create mode 100644 Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt > > diff --git a/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml > new file mode 100644 > index 000000000000..c0f61af3bde4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml > @@ -0,0 +1,49 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +# Copyright (C) 2025 Altera Corporation > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Altera GMII to SGMII Converter > + > +maintainers: > + - Matthew Gerlach <matthew.gerlach@altera.com> > + > +description: > + This binding describes the Altera GMII to SGMII converter. > + > +properties: > + comptatible: typo > + const: altr,gmii-to-sgmii-2.0 > +
On 6/9/25 3:15 PM, Rob Herring wrote: > On Mon, Jun 09, 2025 at 09:37:25AM -0700, Matthew Gerlach wrote: > > Convert the bindings for socfpga-dwmac to yaml. Since the original > > text contained descriptions for two separate nodes, two separate > > yaml files were created. > > > > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> > > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> > > --- > > v4: > > - Change filename from socfpga,dwmac.yaml to altr,socfpga-stmmac.yaml. > > - Updated compatible in select properties and main properties. > > - Fixed clocks so stmmaceth clock is required. > > - Added binding for altr,gmii-to-sgmii. > > - Update MAINTAINERS. > > > > v3: > > - Add missing supported phy-modes. > > > > v2: > > - Add compatible to required. > > - Add descriptions for clocks. > > - Add clock-names. > > - Clean up items: in altr,sysmgr-syscon. > > - Change "additionalProperties: true" to "unevaluatedProperties: false". > > - Add properties needed for "unevaluatedProperties: false". > > - Fix indentation in examples. > > - Drop gmac0: label in examples. > > - Exclude support for Arria10 that is not validating. > > --- > > .../bindings/net/altr,gmii-to-sgmii.yaml | 49 ++++++ > > .../bindings/net/altr,socfpga-stmmac.yaml | 162 ++++++++++++++++++ > > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------ > > MAINTAINERS | 7 +- > > 4 files changed, 217 insertions(+), 58 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml > > altr,gmii-to-sgmii-2.0.yaml The '2.0' in the compatible string refers to a revision of the converter IP. Wouldn't a single yaml be used to describe multiple revisions of the IP, like net/snps,dwmac.yaml? Having the revision number in the filename appears to be unusual. > > > create mode 100644 Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml > > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt > > > > diff --git a/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml > > new file mode 100644 > > index 000000000000..c0f61af3bde4 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml > > @@ -0,0 +1,49 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +# Copyright (C) 2025 Altera Corporation > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Altera GMII to SGMII Converter > > + > > +maintainers: > > + - Matthew Gerlach <matthew.gerlach@altera.com> > > + > > +description: > > + This binding describes the Altera GMII to SGMII converter. > > + > > +properties: > > + comptatible: > > typo I am very surprised by this typo; so, I rechecked. I used the command, make dt_binding_check DT_SCHEMA_FILES=altr,gmii-to-sgmii.yaml, which did not report an error, but I did confirm the bot's error with the command, make dt_binding_check. I will be sure to run the full 'make dt_binding_check' before submitting. Thanks for the feedback, Matthew Gerlach > > > + const: altr,gmii-to-sgmii-2.0 > > +
On Mon, 09 Jun 2025 09:37:25 -0700, Matthew Gerlach wrote: > Convert the bindings for socfpga-dwmac to yaml. Since the original > text contained descriptions for two separate nodes, two separate > yaml files were created. > > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> > --- > v4: > - Change filename from socfpga,dwmac.yaml to altr,socfpga-stmmac.yaml. > - Updated compatible in select properties and main properties. > - Fixed clocks so stmmaceth clock is required. > - Added binding for altr,gmii-to-sgmii. > - Update MAINTAINERS. > > v3: > - Add missing supported phy-modes. > > v2: > - Add compatible to required. > - Add descriptions for clocks. > - Add clock-names. > - Clean up items: in altr,sysmgr-syscon. > - Change "additionalProperties: true" to "unevaluatedProperties: false". > - Add properties needed for "unevaluatedProperties: false". > - Fix indentation in examples. > - Drop gmac0: label in examples. > - Exclude support for Arria10 that is not validating. > --- > .../bindings/net/altr,gmii-to-sgmii.yaml | 49 ++++++ > .../bindings/net/altr,socfpga-stmmac.yaml | 162 ++++++++++++++++++ > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------ > MAINTAINERS | 7 +- > 4 files changed, 217 insertions(+), 58 deletions(-) > create mode 100644 Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.yaml > create mode 100644 Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/net/altr,gmii-to-sgmii.example.dtb: /example-0/phy@ff000240: failed to match any schema with compatible: ['altr,gmii-to-sgmii-2.0'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250609163725.6075-1-matthew.gerlach@altera.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
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