The PCIe slot may have clocks which are explicitly controlled
by the OS, describe the clocks property.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Related to https://lore.kernel.org/all/CAMuHMdUFHKHKfymqa6jwfNnxZTAuH3kbj5WL+-zN=TR6XGd0eA@mail.gmail.com/
---
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 dtschema/schemas/pci/pci-bus-common.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index ca97a00..3c512cf 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -82,6 +82,8 @@ properties:
     items:
       maximum: 255
 
+  clocks: true
+
   external-facing:
     description:
       When present, the port is externally facing. All bridges and endpoints
-- 
2.47.2

On Sat, Jun 07, 2025 at 09:43:24PM +0200, Marek Vasut wrote:
> The PCIe slot may have clocks which are explicitly controlled
> by the OS, describe the clocks property.

The slot can only have 'REFCLK' as per the spec, not any other random clocks.

> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

With that fixed,

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
> Related to https://lore.kernel.org/all/CAMuHMdUFHKHKfymqa6jwfNnxZTAuH3kbj5WL+-zN=TR6XGd0eA@mail.gmail.com/
> ---
> Cc: Bartosz Golaszewski <brgl@bgdev.pl>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>  dtschema/schemas/pci/pci-bus-common.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> index ca97a00..3c512cf 100644
> --- a/dtschema/schemas/pci/pci-bus-common.yaml
> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> @@ -82,6 +82,8 @@ properties:
>      items:
>        maximum: 255
>  
> +  clocks: true
> +
>    external-facing:
>      description:
>        When present, the port is externally facing. All bridges and endpoints
> -- 
> 2.47.2
> 
> 

-- 
மணிவண்ணன் சதாசிவம்

On Wed, Jun 11, 2025 at 06:09:27PM +0530, Manivannan Sadhasivam wrote:
> On Sat, Jun 07, 2025 at 09:43:24PM +0200, Marek Vasut wrote:
> > The PCIe slot may have clocks which are explicitly controlled
> > by the OS, describe the clocks property.
> 
> The slot can only have 'REFCLK' as per the spec, not any other random clocks.
> 
> > 
> > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> 
> With that fixed,
> 
> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Sorry. Wrong tag. Please take this one:

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> 
> - Mani
> 
> > ---
> > Related to https://lore.kernel.org/all/CAMuHMdUFHKHKfymqa6jwfNnxZTAuH3kbj5WL+-zN=TR6XGd0eA@mail.gmail.com/
> > ---
> > Cc: Bartosz Golaszewski <brgl@bgdev.pl>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Conor Dooley <conor+dt@kernel.org>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> > Cc: Magnus Damm <magnus.damm@gmail.com>
> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Cc: Rob Herring <robh@kernel.org>
> > Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: linux-pci@vger.kernel.org
> > Cc: linux-renesas-soc@vger.kernel.org
> > ---
> >  dtschema/schemas/pci/pci-bus-common.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> > index ca97a00..3c512cf 100644
> > --- a/dtschema/schemas/pci/pci-bus-common.yaml
> > +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> > @@ -82,6 +82,8 @@ properties:
> >      items:
> >        maximum: 255
> >  
> > +  clocks: true
> > +
> >    external-facing:
> >      description:
> >        When present, the port is externally facing. All bridges and endpoints
> > -- 
> > 2.47.2
> > 
> > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்

-- 
மணிவண்ணன் சதாசிவம்