[v5] add Voyager board support

[PATCH v5 0/8] add Voyager board support

Posted by Ben Zong-You Xie 4 months, 1 week ago

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].

Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
---
Changelog from v4 to v5:
  - Rebase the series on torvalds/master
  - Clarify the patch dependencies (2 <- 4 <- 5 <- 6) in the patch description

v4: https://lore.kernel.org/all/20250514095350.3765716-1-ben717@andestech.com/

Changelog from v3 to v4:
  - Restore the modification to cache-sets and cache-size in patch 6
  - Do not constrain renesas,r9a07g043f-ax45mp-cache since it's independent to
    this series.
  - Delete the redundant example added by patch 6

v3: https://lore.kernel.org/all/20250513094933.1631493-1-ben717@andestech.com/

Changelog from v2 to v3:
  - Rebase the series on Conor/riscv-soc-for-next
  - Reform patch 6 as suggested by Conor
  - Modify l2_cache's compatible in qilai.dtsi due to patch 6
  - Add Conor's Acked-by tag to patch 4
  - Add Conor's Acked-by tag to patch 5
  - Add Conor's Acked-by tag to patch 9

v2: https://lore.kernel.org/all/20250503151829.605006-5-ben717@andestech.com/

Changelog from v1 to v2:
  - Add detailed descriptions to PLIC_SW and PLMT0
  - Move the aliases node and memory node from qilai.dtsi to qilai-voyager.dts
  - Drop "status = okay" in each CPU node since the status property is by
    default "okay"
  - Reorder the nodes in qilai.dtsi by unit address in ascending order
  - Add myself as the maintainer of Andes's SoC tree
  - Add Rob's Reviewed-by tag to patch 2
  - Add Rob's Acked-by tag to patch 3
  - Add Rob's Acked-by tag to patch 6.

v1: https://lore.kernel.org/all/20250407104937.315783-1-ben717@andestech.com/

---
Ben Zong-You Xie (8):
  riscv: add Andes SoC family Kconfig support
  dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
  dt-bindings: interrupt-controller: add Andes QiLai PLIC
  dt-bindings: interrupt-controller: add Andes machine-level software
    interrupt controller
  dt-bindings: timer: add Andes machine timer
  riscv: dts: andes: add QiLai SoC device tree
  riscv: dts: andes: add Voyager board device tree
  riscv: defconfig: enable Andes SoC

 .../andestech,plicsw.yaml                     |  54 +++++
 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/andes.yaml      |  25 +++
 .../bindings/timer/andestech,plmt0.yaml       |  53 +++++
 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig.errata                     |   2 +-
 arch/riscv/Kconfig.socs                       |   9 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/andes/Makefile            |   2 +
 arch/riscv/boot/dts/andes/qilai-voyager.dts   |  28 +++
 arch/riscv/boot/dts/andes/qilai.dtsi          | 186 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 12 files changed, 370 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
 create mode 100644 arch/riscv/boot/dts/andes/Makefile
 create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
 create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi

--
2.34.1

Re: [PATCH v5 0/8] add Voyager board support

Posted by Conor Dooley 4 months ago

On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> including Andes QiLai SoC. This patch series adds minimal device tree
> files for the QiLai SoC and the Voyager board [1].
> 
> Now only support basic uart drivers to boot up into a basic console. Other
> features will be added later.
> 
> [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Ball is in your court now, after rc1 make a tree and get it in
linux-next, and then send a pr to soc@kernel.org with this new content.
Perhaps the defconfig should go separately, I can take that one if you
want.

Cheers,
Conor.

> ---
> Changelog from v4 to v5:
>   - Rebase the series on torvalds/master
>   - Clarify the patch dependencies (2 <- 4 <- 5 <- 6) in the patch description
> 
> v4: https://lore.kernel.org/all/20250514095350.3765716-1-ben717@andestech.com/
> 
> Changelog from v3 to v4:
>   - Restore the modification to cache-sets and cache-size in patch 6
>   - Do not constrain renesas,r9a07g043f-ax45mp-cache since it's independent to
>     this series.
>   - Delete the redundant example added by patch 6
> 
> v3: https://lore.kernel.org/all/20250513094933.1631493-1-ben717@andestech.com/
> 
> Changelog from v2 to v3:
>   - Rebase the series on Conor/riscv-soc-for-next
>   - Reform patch 6 as suggested by Conor
>   - Modify l2_cache's compatible in qilai.dtsi due to patch 6
>   - Add Conor's Acked-by tag to patch 4
>   - Add Conor's Acked-by tag to patch 5
>   - Add Conor's Acked-by tag to patch 9
> 
> v2: https://lore.kernel.org/all/20250503151829.605006-5-ben717@andestech.com/
> 
> Changelog from v1 to v2:
>   - Add detailed descriptions to PLIC_SW and PLMT0
>   - Move the aliases node and memory node from qilai.dtsi to qilai-voyager.dts
>   - Drop "status = okay" in each CPU node since the status property is by
>     default "okay"
>   - Reorder the nodes in qilai.dtsi by unit address in ascending order
>   - Add myself as the maintainer of Andes's SoC tree
>   - Add Rob's Reviewed-by tag to patch 2
>   - Add Rob's Acked-by tag to patch 3
>   - Add Rob's Acked-by tag to patch 6.
> 
> v1: https://lore.kernel.org/all/20250407104937.315783-1-ben717@andestech.com/
> 
> ---
> Ben Zong-You Xie (8):
>   riscv: add Andes SoC family Kconfig support
>   dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
>   dt-bindings: interrupt-controller: add Andes QiLai PLIC
>   dt-bindings: interrupt-controller: add Andes machine-level software
>     interrupt controller
>   dt-bindings: timer: add Andes machine timer
>   riscv: dts: andes: add QiLai SoC device tree
>   riscv: dts: andes: add Voyager board device tree
>   riscv: defconfig: enable Andes SoC
> 
>  .../andestech,plicsw.yaml                     |  54 +++++
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../devicetree/bindings/riscv/andes.yaml      |  25 +++
>  .../bindings/timer/andestech,plmt0.yaml       |  53 +++++
>  MAINTAINERS                                   |   9 +
>  arch/riscv/Kconfig.errata                     |   2 +-
>  arch/riscv/Kconfig.socs                       |   9 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/andes/Makefile            |   2 +
>  arch/riscv/boot/dts/andes/qilai-voyager.dts   |  28 +++
>  arch/riscv/boot/dts/andes/qilai.dtsi          | 186 ++++++++++++++++++
>  arch/riscv/configs/defconfig                  |   1 +
>  12 files changed, 370 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
>  create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
>  create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
>  create mode 100644 arch/riscv/boot/dts/andes/Makefile
>  create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
>  create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi
> 
> --
> 2.34.1
>

Re: [PATCH v5 0/8] add Voyager board support

Posted by Ben Zong-You Xie 3 months, 4 weeks ago

On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]

> Date: Fri, 6 Jun 2025 17:00:06 +0100
> From: Conor Dooley <conor@kernel.org>
> To: Ben Zong-You Xie <ben717@andestech.com>
> Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
>  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
>  tglx@linutronix.de, daniel.lezcano@linaro.org,
>  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
>  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
>  tim609@andestech.com
> Subject: Re: [PATCH v5 0/8] add Voyager board support
> 
> On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > including Andes QiLai SoC. This patch series adds minimal device tree
> > files for the QiLai SoC and the Voyager board [1].
> > 
> > Now only support basic uart drivers to boot up into a basic console. Other
> > features will be added later.
> > 
> > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> 
> Ball is in your court now, after rc1 make a tree and get it in
> linux-next, and then send a pr to soc@kernel.org with this new content.
> Perhaps the defconfig should go separately, I can take that one if you
> want.
> 
> Cheers,
> Conor.

Hi Conor,

Thanks for your guidance on these patches. I will send a PR to
soc@kernel.org as you suggested.

For the defconfig patch, I'm happy for you to handle it. Just let me
know if there's anything specific you'd like me to include.

Thanks,
Ben

Re: [PATCH v5 0/8] add Voyager board support

Posted by Conor Dooley 3 months, 4 weeks ago

On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > [EXTERNAL MAIL]
> 
> > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > From: Conor Dooley <conor@kernel.org>
> > To: Ben Zong-You Xie <ben717@andestech.com>
> > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> >  tim609@andestech.com
> > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > 
> > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > files for the QiLai SoC and the Voyager board [1].
> > > 
> > > Now only support basic uart drivers to boot up into a basic console. Other
> > > features will be added later.
> > > 
> > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > 
> > Ball is in your court now, after rc1 make a tree and get it in
> > linux-next, and then send a pr to soc@kernel.org with this new content.
> > Perhaps the defconfig should go separately, I can take that one if you
> > want.
> > 
> > Cheers,
> > Conor.
> 
> Hi Conor,
> 
> Thanks for your guidance on these patches. I will send a PR to
> soc@kernel.org as you suggested.
> 
> For the defconfig patch, I'm happy for you to handle it. Just let me
> know if there's anything specific you'd like me to include.

Okay, I picked it up on the basis that you'll send this all to Arnd for
6.17

Re: [PATCH v5 0/8] add Voyager board support

Posted by Conor Dooley 3 months, 4 weeks ago

On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > [EXTERNAL MAIL]
> > 
> > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > From: Conor Dooley <conor@kernel.org>
> > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > >  tim609@andestech.com
> > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > 
> > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > files for the QiLai SoC and the Voyager board [1].
> > > > 
> > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > features will be added later.
> > > > 
> > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > 
> > > Ball is in your court now, after rc1 make a tree and get it in
> > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > Perhaps the defconfig should go separately, I can take that one if you
> > > want.
> > > 
> > > Cheers,
> > > Conor.
> > 
> > Hi Conor,
> > 
> > Thanks for your guidance on these patches. I will send a PR to
> > soc@kernel.org as you suggested.
> > 
> > For the defconfig patch, I'm happy for you to handle it. Just let me
> > know if there's anything specific you'd like me to include.
> 
> Okay, I picked it up on the basis that you'll send this all to Arnd for
> 6.17

Sorry, I think that was really poorly worded. I picked it up on the
basis that you're going to send the other patches in the series to Arnd
for 6.17.

Re: [PATCH v5 0/8] add Voyager board support

Posted by Ben Zong-You Xie 3 months, 3 weeks ago

On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]

> Date: Mon, 9 Jun 2025 17:17:50 +0100
> From: Conor Dooley <conor@kernel.org>
> To: Ben Zong-You Xie <ben717@andestech.com>
> Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
>  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
>  tglx@linutronix.de, daniel.lezcano@linaro.org,
>  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
>  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
>  tim609@andestech.com
> Subject: Re: [PATCH v5 0/8] add Voyager board support
> 
> On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> > On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > > [EXTERNAL MAIL]
> > > 
> > > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > > From: Conor Dooley <conor@kernel.org>
> > > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > > >  tim609@andestech.com
> > > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > > 
> > > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > > files for the QiLai SoC and the Voyager board [1].
> > > > > 
> > > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > > features will be added later.
> > > > > 
> > > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > > 
> > > > Ball is in your court now, after rc1 make a tree and get it in
> > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > > Perhaps the defconfig should go separately, I can take that one if you
> > > > want.
> > > > 
> > > > Cheers,
> > > > Conor.
> > > 
> > > Hi Conor,
> > > 
> > > Thanks for your guidance on these patches. I will send a PR to
> > > soc@kernel.org as you suggested.
> > > 
> > > For the defconfig patch, I'm happy for you to handle it. Just let me
> > > know if there's anything specific you'd like me to include.
> > 
> > Okay, I picked it up on the basis that you'll send this all to Arnd for
> > 6.17
> 
> Sorry, I think that was really poorly worded. I picked it up on the
> basis that you're going to send the other patches in the series to Arnd
> for 6.17.

Hi Conor,

According to the SoC maintainer documentation [1], I should send a
patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
I think I should not sent a PR to the main SoC maintainer. Is that right?

Further, I have two questions about sending a patchset:   
1. Should I send v5 or start a new patchset?
2. Should I continue excluding the defconfig patch, as we discussed
   previously? I think it should be included now.

[1] https://docs.kernel.org/process/maintainer-soc.html#submitting-patches-to-the-main-soc-maintainers

Thanks,
Ben

Re: [PATCH v5 0/8] add Voyager board support

Posted by Conor Dooley 3 months, 3 weeks ago

+CC Arnd,

On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> > [EXTERNAL MAIL]
> 
> > Date: Mon, 9 Jun 2025 17:17:50 +0100
> > From: Conor Dooley <conor@kernel.org>
> > To: Ben Zong-You Xie <ben717@andestech.com>
> > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> >  tim609@andestech.com
> > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > 
> > On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> > > On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > > > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > > > [EXTERNAL MAIL]
> > > > 
> > > > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > > > From: Conor Dooley <conor@kernel.org>
> > > > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > > > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > > > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > > > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > > > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > > > >  tim609@andestech.com
> > > > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > > > 
> > > > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > > > files for the QiLai SoC and the Voyager board [1].
> > > > > > 
> > > > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > > > features will be added later.
> > > > > > 
> > > > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > > > 
> > > > > Ball is in your court now, after rc1 make a tree and get it in
> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > > > Perhaps the defconfig should go separately, I can take that one if you
> > > > > want.

> > > > Thanks for your guidance on these patches. I will send a PR to
> > > > soc@kernel.org as you suggested.
> > > > 
> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
> > > > know if there's anything specific you'd like me to include.
> > > 
> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
> > > 6.17
> > 
> > Sorry, I think that was really poorly worded. I picked it up on the
> > basis that you're going to send the other patches in the series to Arnd
> > for 6.17.
> 
> According to the SoC maintainer documentation [1], I should send a
> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
> I think I should not sent a PR to the main SoC maintainer. Is that right?

I think you can send a PR and not worry about it.

> Further, I have two questions about sending a patchset:   
> 1. Should I send v5 or start a new patchset?
> 2. Should I continue excluding the defconfig patch, as we discussed
>    previously? I think it should be included now.

Arnd, you okay with a defconfig in the same branch as the dts/core
bindings for a new platform? I'll happily drop it from by branch if it
can all go as one.

Re: [PATCH v5 0/8] add Voyager board support

Posted by Arnd Bergmann 3 months ago

On Wed, Jun 11, 2025, at 18:21, Conor Dooley wrote:
> On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
>> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
>> > > > > 
>> > > > > Ball is in your court now, after rc1 make a tree and get it in
>> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
>> > > > > Perhaps the defconfig should go separately, I can take that one if you
>> > > > > want.
>
>> > > > Thanks for your guidance on these patches. I will send a PR to
>> > > > soc@kernel.org as you suggested.
>> > > > 
>> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
>> > > > know if there's anything specific you'd like me to include.
>> > > 
>> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
>> > > 6.17
>> > 
>> > Sorry, I think that was really poorly worded. I picked it up on the
>> > basis that you're going to send the other patches in the series to Arnd
>> > for 6.17.
>> 
>> According to the SoC maintainer documentation [1], I should send a
>> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
>> I think I should not sent a PR to the main SoC maintainer. Is that right?
>
> I think you can send a PR and not worry about it.
>
>> Further, I have two questions about sending a patchset:   
>> 1. Should I send v5 or start a new patchset?
>> 2. Should I continue excluding the defconfig patch, as we discussed
>>    previously? I think it should be included now.
>
> Arnd, you okay with a defconfig in the same branch as the dts/core
> bindings for a new platform? I'll happily drop it from by branch if it
> can all go as one.

Sorry I missed your question earlier, I finally got to it now as
I am going through the pull requests in patchwork.

Having the defconfig, MAINTAINERS and Kconfig updates in the branch
for a new platform is fine, in this case it makes sense to keep
everything together.

I'm also planning to have multiple new SoC targets in 6.17 and
would put them into a separate branch that does not contain the
dts changes for the existing SoCs.

For the pull request that Ben sent, there were a couple of
mistakes, I'll reply on that separately. It probably would made
more sense to send the patches to soc@lists.linux.dev (note
that the soc@kernel.org address got renamed but they still
both work) than to send a pull request this time.

     Arnd

Re: [PATCH v5 0/8] add Voyager board support

Posted by Conor Dooley 3 months ago

On Thu, Jul 03, 2025 at 05:32:08PM +0200, Arnd Bergmann wrote:
> On Wed, Jun 11, 2025, at 18:21, Conor Dooley wrote:
> > On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
> >> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> >> > > > > 
> >> > > > > Ball is in your court now, after rc1 make a tree and get it in
> >> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> >> > > > > Perhaps the defconfig should go separately, I can take that one if you
> >> > > > > want.
> >
> >> > > > Thanks for your guidance on these patches. I will send a PR to
> >> > > > soc@kernel.org as you suggested.
> >> > > > 
> >> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
> >> > > > know if there's anything specific you'd like me to include.
> >> > > 
> >> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
> >> > > 6.17
> >> > 
> >> > Sorry, I think that was really poorly worded. I picked it up on the
> >> > basis that you're going to send the other patches in the series to Arnd
> >> > for 6.17.
> >> 
> >> According to the SoC maintainer documentation [1], I should send a
> >> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
> >> I think I should not sent a PR to the main SoC maintainer. Is that right?
> >
> > I think you can send a PR and not worry about it.
> >
> >> Further, I have two questions about sending a patchset:   
> >> 1. Should I send v5 or start a new patchset?
> >> 2. Should I continue excluding the defconfig patch, as we discussed
> >>    previously? I think it should be included now.
> >
> > Arnd, you okay with a defconfig in the same branch as the dts/core
> > bindings for a new platform? I'll happily drop it from by branch if it
> > can all go as one.
> 
> Sorry I missed your question earlier, I finally got to it now as
> I am going through the pull requests in patchwork.

Yeah, I've been kinda out of it lately. Ordinarily I'd have pinged you
on IRC or something, but instead this thread has just been sitting in my
devicetree mail folder.

> Having the defconfig, MAINTAINERS and Kconfig updates in the branch
> for a new platform is fine, in this case it makes sense to keep
> everything together.

Okay, I have dropped it from my config branch.

> I'm also planning to have multiple new SoC targets in 6.17 and
> would put them into a separate branch that does not contain the
> dts changes for the existing SoCs.
> 
> For the pull request that Ben sent, there were a couple of
> mistakes, I'll reply on that separately. It probably would made
> more sense to send the patches to soc@lists.linux.dev (note
> that the soc@kernel.org address got renamed but they still
> both work) than to send a pull request this time.

Is that a general comment btw? If there are other people coming in with
new platforms should I ask them to send patches to soc@lists.linux.dev
instead of a PR for their first time?

Re: [PATCH v5 0/8] add Voyager board support

Posted by Arnd Bergmann 3 months ago

On Thu, Jul 3, 2025, at 17:53, Conor Dooley wrote:
> On Thu, Jul 03, 2025 at 05:32:08PM +0200, Arnd Bergmann wrote:
>> On Wed, Jun 11, 2025, at 18:21, Conor Dooley wrote:
>>
>> I'm also planning to have multiple new SoC targets in 6.17 and
>> would put them into a separate branch that does not contain the
>> dts changes for the existing SoCs.
>> 
>> For the pull request that Ben sent, there were a couple of
>> mistakes, I'll reply on that separately. It probably would made
>> more sense to send the patches to soc@lists.linux.dev (note
>> that the soc@kernel.org address got renamed but they still
>> both work) than to send a pull request this time.
>
> Is that a general comment btw? If there are other people coming in with
> new platforms should I ask them to send patches to soc@lists.linux.dev
> instead of a PR for their first time?

It's mainly about how comfortable the new maintainers are with
the process, in this case it was clearly a bit too much for
Ben to get right at the first time, but others are more
experienced with sending pull requests to kernel maintainers
already. Since the patches individually are all fine, I could
have just applied them, but the PR ended up having too many
mistakes.

The one thing that is special for a new platform is that the branch
can mix things that would otherwise be separate pull requests.
Sending this as patches means that I have more flexibility to
apply it either into a branch for the new platform or split it
up as normal.

    Arnd