From: Abhinav Kumar <quic_abhinavk@quicinc.com>
On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
the display port controller can support more than one pixel stream
(multi-stream transport).
To support MST on such chipsets, add the binding for stream 1 pixel
clock for display port controller.
Since this mode is not supported on all chipsets, add exception
rules and min/max items to clearly mark which chipsets support
only SST mode (single stream) and which ones support MST.
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
.../bindings/display/msm/dp-controller.yaml | 36 ++++++++++++++++++++--
.../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++--
.../bindings/display/msm/qcom,sar2130p-mdss.yaml | 9 ++++--
.../bindings/display/msm/qcom,sc7280-mdss.yaml | 9 ++++--
.../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
5 files changed, 56 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index a63efd8de42c..81ffc141e00d 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -54,25 +54,31 @@ properties:
maxItems: 1
clocks:
+ minItems: 5
items:
- description: AHB clock to enable register access
- description: Display Port AUX clock
- description: Display Port Link clock
- description: Link interface clock between DP and PHY
- - description: Display Port Pixel clock
+ - description: Display Port stream 0 Pixel clock
+ - description: Display Port stream 1 Pixel clock
clock-names:
+ minItems: 5
items:
- const: core_iface
- const: core_aux
- const: ctrl_link
- const: ctrl_link_iface
- const: stream_pixel
+ - const: stream_1_pixel
assigned-clocks:
+ minItems: 2
items:
- description: link clock source
- - description: pixel clock source
+ - description: stream 0 pixel clock source
+ - description: stream 1 pixel clock source
phys:
maxItems: 1
@@ -174,6 +180,32 @@ allOf:
required:
- "#sound-dai-cells"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-dp
+ - qcom,sm8150-dp
+ - qcom,sc8180x-dp
+ - qcom,sc8280xp-dp
+ - qcom,sm8350-dp
+ - qcom,sm8450-dp
+ - qcom,sm8650-dp
+ - qcom,sa8775p-dp
+ - qcom,x1e80100-dp
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ maxItems: 6
+
+ else:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index 951e446dc828..4fdb78a400c4 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -384,15 +384,18 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
- <&dispcc_mdss_dptx0_pixel0_clk_src>;
+ <&dispcc_mdss_dptx0_pixel0_clk_src>,
+ <&dispcc_mdss_dptx0_pixel1_clk_src>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
index a1f5a6bd328e..e1b2788e2710 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
@@ -207,15 +207,18 @@ examples:
<&dispcc_disp_cc_mdss_dptx0_aux_clk>,
<&dispcc_disp_cc_mdss_dptx0_link_clk>,
<&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
- <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>;
+ <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>,
+ <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
- <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>;
+ <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>,
+ <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
index 7842ef274258..445224758d34 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
@@ -380,14 +380,17 @@ examples:
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
phys = <&dp_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
index 791de8a277cb..1ade6aed2e20 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
@@ -183,11 +183,13 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
<&dispcc_mdss_dptx0_pixel0_clk_src>;
--
2.49.0On Fri, May 30, 2025 at 10:47:27AM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhinavk@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > To support MST on such chipsets, add the binding for stream 1 pixel > clock for display port controller. If I remember correctly, some of these chipsets support more than 2 MST streams, which means more than 1 additional pixel clock. Could you please clarify this? If so, can we please describe all clocks, so that we don't have to return back to the topic. > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 ++++++++++++++++++++-- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 9 ++++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 9 ++++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 5 files changed, 56 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index a63efd8de42c..81ffc141e00d 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -54,25 +54,31 @@ properties: > maxItems: 1 > > clocks: > + minItems: 5 > items: > - description: AHB clock to enable register access > - description: Display Port AUX clock > - description: Display Port Link clock > - description: Link interface clock between DP and PHY > - - description: Display Port Pixel clock > + - description: Display Port stream 0 Pixel clock > + - description: Display Port stream 1 Pixel clock > > clock-names: > + minItems: 5 > items: > - const: core_iface > - const: core_aux > - const: ctrl_link > - const: ctrl_link_iface > - const: stream_pixel > + - const: stream_1_pixel > > assigned-clocks: > + minItems: 2 > items: > - description: link clock source > - - description: pixel clock source > + - description: stream 0 pixel clock source > + - description: stream 1 pixel clock source > > phys: > maxItems: 1 > @@ -174,6 +180,32 @@ allOf: > required: > - "#sound-dai-cells" > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sc7280-dp > + - qcom,sm8150-dp > + - qcom,sc8180x-dp > + - qcom,sc8280xp-dp > + - qcom,sm8350-dp > + - qcom,sm8450-dp > + - qcom,sm8650-dp > + - qcom,sa8775p-dp > + - qcom,x1e80100-dp Let's get this list sorted alphabetically. Also, do we need to list all those entries? Some of those use fallback compatible to qcom,sm8350-dp, so it should be enough to list just that entry for those. > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + > + else: > + properties: > + clocks: > + minItems: 5 > + maxItems: 5 > + > additionalProperties: false > > examples: -- With best wishes Dmitry
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