[v2] Relax max-link-speed check to support PCIe Gen5/Gen6

[PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

Posted by Hans Zhang 6 months, 3 weeks ago

Update the device tree binding documentation for PCI to include
PCIe Gen5 and Gen6 support in the `max-link-speed` property.
The original documentation limited the value to 1~4 (Gen1~Gen4),
but the kernel now supports up to Gen6. This change ensures the
documentation aligns with the actual code implementation.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 dtschema/schemas/pci/pci-bus-common.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index ca97a00..413ef05 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -121,7 +121,7 @@ properties:
       unnecessary operation for unsupported link speed, for instance, trying to
       do training for unsupported link speed, etc.
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [ 1, 2, 3, 4 ]
+    enum: [ 1, 2, 3, 4, 5, 6 ]
 
   num-lanes:
     description: The number of PCIe lanes
-- 
2.25.1

Re: [PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

Posted by Manivannan Sadhasivam 6 months ago

On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote:
> Update the device tree binding documentation for PCI to include
> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
> The original documentation limited the value to 1~4 (Gen1~Gen4),
> but the kernel now supports up to Gen6. This change ensures the
> documentation aligns with the actual code implementation.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
>  dtschema/schemas/pci/pci-bus-common.yaml | 2 +-

As Rob commented in v1, this file lives in dtschema project. So update it there:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml

- Mani

>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> index ca97a00..413ef05 100644
> --- a/dtschema/schemas/pci/pci-bus-common.yaml
> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> @@ -121,7 +121,7 @@ properties:
>        unnecessary operation for unsupported link speed, for instance, trying to
>        do training for unsupported link speed, etc.
>      $ref: /schemas/types.yaml#/definitions/uint32
> -    enum: [ 1, 2, 3, 4 ]
> +    enum: [ 1, 2, 3, 4, 5, 6 ]
>  
>    num-lanes:
>      description: The number of PCIe lanes
> -- 
> 2.25.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

Posted by Hans Zhang 6 months ago


On 2025/6/18 00:45, Manivannan Sadhasivam wrote:
> On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote:
>> Update the device tree binding documentation for PCI to include
>> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
>> The original documentation limited the value to 1~4 (Gen1~Gen4),
>> but the kernel now supports up to Gen6. This change ensures the
>> documentation aligns with the actual code implementation.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>>   dtschema/schemas/pci/pci-bus-common.yaml | 2 +-
> 
> As Rob commented in v1, this file lives in dtschema project. So update it there:
> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml
> 

Dear Mani,

I made the patch based on the latest dtschema code pulled from github.

Also, I saw similar submissions as follows:
https://lore.kernel.org/linux-pci/advhonmqnxm4s6r3cl7ll5y3jfc566fcjvetvlzvy7bztzetev@t75xmo5fktde/

I don't know if Rob obtained this patch from here and then applied it to 
the dtschema project? Is there still a special process to submit this patch?


Dear Rob,

Can you apply this patch directly to the dtschema project?

Best regards,
Hans

> - Mani
> 
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
>> index ca97a00..413ef05 100644
>> --- a/dtschema/schemas/pci/pci-bus-common.yaml
>> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
>> @@ -121,7 +121,7 @@ properties:
>>         unnecessary operation for unsupported link speed, for instance, trying to
>>         do training for unsupported link speed, etc.
>>       $ref: /schemas/types.yaml#/definitions/uint32
>> -    enum: [ 1, 2, 3, 4 ]
>> +    enum: [ 1, 2, 3, 4, 5, 6 ]
>>   
>>     num-lanes:
>>       description: The number of PCIe lanes
>> -- 
>> 2.25.1
>>
>

Re: [PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

Posted by Hans Zhang 5 months, 2 weeks ago


On 2025/6/18 22:22, Hans Zhang wrote:
> 
> 
> On 2025/6/18 00:45, Manivannan Sadhasivam wrote:
>> On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote:
>>> Update the device tree binding documentation for PCI to include
>>> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
>>> The original documentation limited the value to 1~4 (Gen1~Gen4),
>>> but the kernel now supports up to Gen6. This change ensures the
>>> documentation aligns with the actual code implementation.
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>>   dtschema/schemas/pci/pci-bus-common.yaml | 2 +-
>>
>> As Rob commented in v1, this file lives in dtschema project. So update 
>> it there:
>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml
>>
> 
> Dear Mani,
> 
> I made the patch based on the latest dtschema code pulled from github.
> 
> Also, I saw similar submissions as follows:
> https://lore.kernel.org/linux-pci/advhonmqnxm4s6r3cl7ll5y3jfc566fcjvetvlzvy7bztzetev@t75xmo5fktde/
> 
> I don't know if Rob obtained this patch from here and then applied it to 
> the dtschema project? Is there still a special process to submit this 
> patch?
> 
> 
> Dear Rob,
> 
> Can you apply this patch directly to the dtschema project?
> 

Dear Rob,

Gentle ping.

Best regards,
Hans

> Best regards,
> Hans
> 
>> - Mani
>>
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml 
>>> b/dtschema/schemas/pci/pci-bus-common.yaml
>>> index ca97a00..413ef05 100644
>>> --- a/dtschema/schemas/pci/pci-bus-common.yaml
>>> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
>>> @@ -121,7 +121,7 @@ properties:
>>>         unnecessary operation for unsupported link speed, for 
>>> instance, trying to
>>>         do training for unsupported link speed, etc.
>>>       $ref: /schemas/types.yaml#/definitions/uint32
>>> -    enum: [ 1, 2, 3, 4 ]
>>> +    enum: [ 1, 2, 3, 4, 5, 6 ]
>>>     num-lanes:
>>>       description: The number of PCIe lanes
>>> -- 
>>> 2.25.1
>>>
>>