.../bindings/net/socfpga,dwmac.yaml | 148 ++++++++++++++++++ .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------- 2 files changed, 148 insertions(+), 57 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/socfpga,dwmac.yaml delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
From: Mun Yew Tham <mun.yew.tham@altera.com>
Convert the bindings for socfpga-dwmac to yaml.
Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v2:
- Add compatible to required.
- Add descriptions for clocks.
- Add clock-names.
- Clean up items: in altr,sysmgr-syscon.
- Change "additionalProperties: true" to "unevaluatedProperties: false".
- Add properties needed for "unevaluatedProperties: false".
- Fix indentation in examples.
- Drop gmac0: label in examples.
- Exclude support for Arria10 that is not validating.
---
.../bindings/net/socfpga,dwmac.yaml | 148 ++++++++++++++++++
.../devicetree/bindings/net/socfpga-dwmac.txt | 57 -------
2 files changed, 148 insertions(+), 57 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
diff --git a/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
new file mode 100644
index 000000000000..a02175838fba
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/socfpga,dwmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA SoC DWMAC controller
+
+maintainers:
+ - Matthew Gerlach <matthew.gerlach@altera.com>
+
+description:
+ This binding describes the Altera SOCFPGA SoC implementation of the
+ Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
+ of chips.
+ # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
+ # does not validate against net/snps,dwmac.yaml.
+
+select:
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: altr,socfpga-stmmac
+ - const: snps,dwmac-3.70a
+ - const: snps,dwmac
+ - items:
+ - const: altr,socfpga-stmmac-a10-s10
+ - const: snps,dwmac-3.74a
+ - const: snps,dwmac
+
+ required:
+ - compatible
+ - altr,sysmgr-syscon
+
+properties:
+ clocks:
+ minItems: 1
+ items:
+ - description: GMAC main clock
+ - description:
+ PTP reference clock. This clock is used for programming the
+ Timestamp Addend Register. If not passed then the system
+ clock will be used and this is fine on some platforms.
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ contains:
+ enum:
+ - stmmaceth
+ - ptp_ref
+
+ iommus:
+ maxItems: 1
+
+ phy-mode:
+ enum:
+ - rgmii
+ - sgmii
+ - gmii
+
+ rxc-skew-ps:
+ description: Skew control of RXC pad
+
+ rxd0-skew-ps:
+ description: Skew control of RX data 0 pad
+
+ rxd1-skew-ps:
+ description: Skew control of RX data 1 pad
+
+ rxd2-skew-ps:
+ description: Skew control of RX data 2 pad
+
+ rxd3-skew-ps:
+ description: Skew control of RX data 3 pad
+
+ rxdv-skew-ps:
+ description: Skew control of RX CTL pad
+
+ txc-skew-ps:
+ description: Skew control of TXC pad
+
+ txen-skew-ps:
+ description: Skew control of TXC pad
+
+ altr,emac-splitter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the emac splitter soft IP node if DWMAC
+ controller is connected an emac splitter.
+
+ altr,f2h_ptp_ref_clk:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to Precision Time Protocol reference clock. This clock is
+ common to gmac instances and defaults to osc1.
+
+ altr,gmii-to-sgmii-converter:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be the phandle to the gmii to sgmii converter soft IP.
+
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Should be the phandle to the system manager node that encompass
+ the glue register, the register offset, and the register shift.
+ On Cyclone5/Arria5, the register shift represents the PHY mode
+ bits, while on the Arria10/Stratix10/Agilex platforms, the
+ register shift represents bit for each emac to enable/disable
+ signals from the FPGA fabric to the EMAC modules.
+ items:
+ - items:
+ - description: phandle to the system manager node
+ - description: offset of the control register
+ - description: shift within the control register
+
+patternProperties:
+ "^mdio[0-9]$":
+ type: object
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ethernet@ff700000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
+ "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+ reg = <0xff700000 0x2000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
+ clocks = <&emac_0_clk>;
+ clock-names = "stmmaceth";
+ phy-mode = "sgmii";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
deleted file mode 100644
index 612a8e8abc88..000000000000
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Altera SOCFPGA SoC DWMAC controller
-
-This is a variant of the dwmac/stmmac driver an inherits all descriptions
-present in Documentation/devicetree/bindings/net/stmmac.txt.
-
-The device node has additional properties:
-
-Required properties:
- - compatible : For Cyclone5/Arria5 SoCs it should contain
- "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
- "altr,socfpga-stmmac-a10-s10".
- Along with "snps,dwmac" and any applicable more detailed
- designware version numbers documented in stmmac.txt
- - altr,sysmgr-syscon : Should be the phandle to the system manager node that
- encompasses the glue register, the register offset, and the register shift.
- On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
- on the Arria10/Stratix10/Agilex platforms, the register shift represents
- bit for each emac to enable/disable signals from the FPGA fabric to the
- EMAC modules.
- - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
- for ptp ref clk. This affects all emacs as the clock is common.
-
-Optional properties:
-altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
- DWMAC controller is connected emac splitter.
-phy-mode: The phy mode the ethernet operates in
-altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
-
-This device node has additional phandle dependency, the sgmii converter:
-
-Required properties:
- - compatible : Should be altr,gmii-to-sgmii-2.0
- - reg-names : Should be "eth_tse_control_port"
-
-Example:
-
-gmii_to_sgmii_converter: phy@100000240 {
- compatible = "altr,gmii-to-sgmii-2.0";
- reg = <0x00000001 0x00000240 0x00000008>,
- <0x00000001 0x00000200 0x00000040>;
- reg-names = "eth_tse_control_port";
- clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
- clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
-};
-
-gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x60 0>;
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
- phy-mode = "sgmii";
- altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
-};
--
2.35.3Hello Matthew, On Wed, 28 May 2025 07:46:50 -0700 Matthew Gerlach <matthew.gerlach@altera.com> wrote: > From: Mun Yew Tham <mun.yew.tham@altera.com> > > Convert the bindings for socfpga-dwmac to yaml. Oh nice ! Thanks for doing that ! I had some very distant plans to do that at some point, but it was way down my priority list :( I'll try to help the best I can ! > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> > --- > v2: > - Add compatible to required. > - Add descriptions for clocks. > - Add clock-names. > - Clean up items: in altr,sysmgr-syscon. > - Change "additionalProperties: true" to "unevaluatedProperties: false". > - Add properties needed for "unevaluatedProperties: false". > - Fix indentation in examples. > - Drop gmac0: label in examples. > - Exclude support for Arria10 that is not validating. > --- > .../bindings/net/socfpga,dwmac.yaml | 148 ++++++++++++++++++ > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------- > 2 files changed, 148 insertions(+), 57 deletions(-) > create mode 100644 Documentation/devicetree/bindings/net/socfpga,dwmac.yaml > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt > > diff --git a/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml > new file mode 100644 > index 000000000000..a02175838fba > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml > @@ -0,0 +1,148 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/socfpga,dwmac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Altera SOCFPGA SoC DWMAC controller > + > +maintainers: > + - Matthew Gerlach <matthew.gerlach@altera.com> > + > +description: > + This binding describes the Altera SOCFPGA SoC implementation of the > + Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families > + of chips. > + # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that > + # does not validate against net/snps,dwmac.yaml. > + > +select: > + properties: > + compatible: > + oneOf: > + - items: > + - const: altr,socfpga-stmmac > + - const: snps,dwmac-3.70a > + - const: snps,dwmac > + - items: > + - const: altr,socfpga-stmmac-a10-s10 > + - const: snps,dwmac-3.74a > + - const: snps,dwmac > + > + required: > + - compatible > + - altr,sysmgr-syscon > + > +properties: > + clocks: > + minItems: 1 > + items: > + - description: GMAC main clock > + - description: > + PTP reference clock. This clock is used for programming the > + Timestamp Addend Register. If not passed then the system > + clock will be used and this is fine on some platforms. > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + contains: > + enum: > + - stmmaceth > + - ptp_ref > + > + iommus: > + maxItems: 1 > + > + phy-mode: > + enum: > + - rgmii You're missing rgmii-id, rgmii-rxid and rgmii-txid > + - sgmii SGMII is only supported when we have the optional altr,gmii-to-sgmii-converter phandle, but I am pretty bad at writing binding, I don't really know how to express this kind of constraint :/ 1000base-x is also supported if the gmii-to-sgmii adapter supports it as well, by having a TSE PCS (Lynx) included. > + - gmii rmii and mii are also supported, it would make sense to add it here. Maxime
On 5/28/25 8:06 AM, Maxime Chevallier wrote: > Hello Matthew, > > On Wed, 28 May 2025 07:46:50 -0700 > Matthew Gerlach <matthew.gerlach@altera.com> wrote: > > > From: Mun Yew Tham <mun.yew.tham@altera.com> > > > > Convert the bindings for socfpga-dwmac to yaml. > > Oh nice ! Thanks for doing that ! I had some very distant plans to do > that at some point, but it was way down my priority list :( I'll try to > help the best I can ! All help is greatly appreciated. I've been trying my best to fix as many socfpga schema check errors as possible. > > > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com> > > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> > > --- > > v2: > > - Add compatible to required. > > - Add descriptions for clocks. > > - Add clock-names. > > - Clean up items: in altr,sysmgr-syscon. > > - Change "additionalProperties: true" to "unevaluatedProperties: false". > > - Add properties needed for "unevaluatedProperties: false". > > - Fix indentation in examples. > > - Drop gmac0: label in examples. > > - Exclude support for Arria10 that is not validating. > > --- > > .../bindings/net/socfpga,dwmac.yaml | 148 ++++++++++++++++++ > > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ------- > > 2 files changed, 148 insertions(+), 57 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/net/socfpga,dwmac.yaml > > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt > > > > diff --git a/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml > > new file mode 100644 > > index 000000000000..a02175838fba > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml > > @@ -0,0 +1,148 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/socfpga,dwmac.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Altera SOCFPGA SoC DWMAC controller > > + > > +maintainers: > > + - Matthew Gerlach <matthew.gerlach@altera.com> > > + > > +description: > > + This binding describes the Altera SOCFPGA SoC implementation of the > > + Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families > > + of chips. > > + # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that > > + # does not validate against net/snps,dwmac.yaml. > > + > > +select: > > + properties: > > + compatible: > > + oneOf: > > + - items: > > + - const: altr,socfpga-stmmac > > + - const: snps,dwmac-3.70a > > + - const: snps,dwmac > > + - items: > > + - const: altr,socfpga-stmmac-a10-s10 > > + - const: snps,dwmac-3.74a > > + - const: snps,dwmac > > + > > + required: > > + - compatible > > + - altr,sysmgr-syscon > > + > > +properties: > > + clocks: > > + minItems: 1 > > + items: > > + - description: GMAC main clock > > + - description: > > + PTP reference clock. This clock is used for programming the > > + Timestamp Addend Register. If not passed then the system > > + clock will be used and this is fine on some platforms. > > + > > + clock-names: > > + minItems: 1 > > + maxItems: 2 > > + contains: > > + enum: > > + - stmmaceth > > + - ptp_ref > > + > > + iommus: > > + maxItems: 1 > > + > > + phy-mode: > > + enum: > > + - rgmii > > You're missing rgmii-id, rgmii-rxid and rgmii-txid Thanks for pointing out more supported phy modes. > > > + - sgmii > > SGMII is only supported when we have the optional > altr,gmii-to-sgmii-converter phandle, but I am pretty bad at writing > binding, I don't really know how to express this kind of constraint :/ > > 1000base-x is also supported if the gmii-to-sgmii adapter supports it > as well, by having a TSE PCS (Lynx) included. Thanks for highlighting the constraint. I'm having difficulties figuring out how to express a couple of constraints (see TODO above). > > > + - gmii > > rmii and mii are also supported, it would make sense to add it > here. I will add rmii and mii as well. > > Maxime Thanks for the review, Matthew Gerlach
> > + phy-mode: > > + enum: > > + - rgmii > > You're missing rgmii-id, rgmii-rxid and rgmii-txid And it is unlikely anybody actually needs rgmii. rgmii-id should be the most used rgmii variant. Andrew
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