EDAC/altera: Use correct width with writes to INTTEST register.

[PATCH] EDAC/altera: Use correct width with writes to INTTEST register.

Posted by Matthew Gerlach 6 months, 3 weeks ago

From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

On SoCFPGA platform INTTEST register only supports 16-bit write based on
the HW design, writing 32-bit to INTTEST register triggers SError to CPU.
Use 16-bit write for INITTEST register.

Fixes: c7b4be8db8bc ("EDAC, altera: Add Arria10 OCRAM ECC support")
Cc: stable@kernel.org
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 drivers/edac/altera_edac.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 20333608b983..cae52c654a15 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1746,9 +1746,9 @@ altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
 
 	local_irq_save(flags);
 	if (trig_type == ALTR_UE_TRIGGER_CHAR)
-		writel(priv->ue_set_mask, set_addr);
+		writew(priv->ue_set_mask, set_addr);
 	else
-		writel(priv->ce_set_mask, set_addr);
+		writew(priv->ce_set_mask, set_addr);
 
 	/* Ensure the interrupt test bits are set */
 	wmb();
@@ -1778,7 +1778,7 @@ altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
 
 	local_irq_save(flags);
 	if (trig_type == ALTR_UE_TRIGGER_CHAR) {
-		writel(priv->ue_set_mask, set_addr);
+		writew(priv->ue_set_mask, set_addr);
 	} else {
 		/* Setup read/write of 4 bytes */
 		writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
-- 
2.35.3

Re: [PATCH] EDAC/altera: Use correct width with writes to INTTEST register.

Posted by Borislav Petkov 6 months, 3 weeks ago

On Tue, May 27, 2025 at 07:57:07AM -0700, Matthew Gerlach wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> On SoCFPGA platform INTTEST register only supports 16-bit write based on
> the HW design, writing 32-bit to INTTEST register triggers SError to CPU.
> Use 16-bit write for INITTEST register.

For the future, please run this text through AI so that it can massage the
formulations into proper English:

    On the SoCFPGA platform, the INTTEST register supports only 16-bit writes.
    A 32-bit write triggers an SError to the CPU so do 16-bit accesses only.

> Fixes: c7b4be8db8bc ("EDAC, altera: Add Arria10 OCRAM ECC support")
> Cc: stable@kernel.org
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
>  drivers/edac/altera_edac.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH] EDAC/altera: Use correct width with writes to INTTEST register.

Posted by Matthew Gerlach 6 months, 3 weeks ago

On 5/29/25 8:41 AM, Borislav Petkov wrote:
> On Tue, May 27, 2025 at 07:57:07AM -0700, Matthew Gerlach wrote:
> > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> > 
> > On SoCFPGA platform INTTEST register only supports 16-bit write based on
> > the HW design, writing 32-bit to INTTEST register triggers SError to CPU.
> > Use 16-bit write for INITTEST register.
>
> For the future, please run this text through AI so that it can massage the
> formulations into proper English:
Great suggestion! With hindsight it should be an obvious suggestion.
>
>      On the SoCFPGA platform, the INTTEST register supports only 16-bit writes.
>      A 32-bit write triggers an SError to the CPU so do 16-bit accesses only.
>
> > Fixes: c7b4be8db8bc ("EDAC, altera: Add Arria10 OCRAM ECC support")
> > Cc: stable@kernel.org
> > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> > ---
> >  drivers/edac/altera_edac.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
>
> Applied, thanks.

Thanks,

Matthew

>

Re: [PATCH] EDAC/altera: Use correct width with writes to INTTEST register.

Posted by Dinh Nguyen 6 months, 3 weeks ago

On 5/27/25 09:57, Matthew Gerlach wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> On SoCFPGA platform INTTEST register only supports 16-bit write based on
> the HW design, writing 32-bit to INTTEST register triggers SError to CPU.
> Use 16-bit write for INITTEST register.
> 
> Fixes: c7b4be8db8bc ("EDAC, altera: Add Arria10 OCRAM ECC support")
> Cc: stable@kernel.org
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
>   drivers/edac/altera_edac.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 

Acked-by: Dinh Nguyen <dinguyen@kernel.org>