This series adds document, phy, configs support for PCIe in QCS615.

This series depend on the dt-bindings change
https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
Have following changes:
	- Add a new Document the QCS615 PCIe Controller
	- Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence.
	- Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc.

Changes in v5:
- Drop qcs615-pcie.yaml and use sm8150, as qcs615 is the downgraded
  version of sm8150, which can share the same yaml.
- Drop compatible enrty in driver and use sm8150's enrty (Krzysztof)
- Fix the DT format problem (Konrad)
- Link to v4: https://lore.kernel.org/all/20250507031559.4085159-1-quic_ziyuzhan@quicinc.com/

Changes in v4:
- Fixed compile error found by kernel test robot(Krzysztof)
- Update DT format (Konrad & Krzysztof)
- Remove QCS8550 compatible use QCS615 compatible only (Konrad)
- Update phy dt bindings to fix the dtb check errors.
- Link to v3: https://lore.kernel.org/all/20250310065613.151598-1-quic_ziyuzhan@quicinc.com/

Changes in v3:
- Update qcs615 dt-bindings to fit the qcom-soc.yaml (Krzysztof & Dmitry)
- Removed the driver patch and using fallback method (Mani)
- Update DT format, keep it same with the x1e801000.dtsi (Konrad)
- Update DT commit message (Bojor)
- Link to v2: https://lore.kernel.org/all/20241122023314.1616353-1-quic_ziyuzhan@quicinc.com/

Changes in v2:
- Update commit message for qcs615 phy
- Update qcs615 phy, using lowercase hex
- Removed redundant function
- split the soc dtsi and the platform dts into two changes
- Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/

Krishna chaitanya chundru (2):
  arm64: dts: qcom: qcs615: enable pcie
  arm64: dts: qcom: qcs615-ride: Enable PCIe interface

Ziyue Zhang (2):
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
    for QCS615
  dt-bindings: PCI: qcom,pcie-sm8150: document qcs615

 .../bindings/pci/qcom,pcie-sm8150.yaml        |   7 +-
 .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |   2 +-
 arch/arm64/boot/dts/qcom/qcs615-ride.dts      |  42 +++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi          | 146 ++++++++++++++++++
 4 files changed, 195 insertions(+), 2 deletions(-)


base-commit: ac12494a238dba00fe8d1459fcf565f9877960f1
-- 
2.34.1

On 5/27/2025 3:20 PM, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS615.
>
> This series depend on the dt-bindings change
> https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
> Have following changes:
> 	- Add a new Document the QCS615 PCIe Controller
> 	- Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence.
> 	- Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc.
>
> Changes in v5:
> - Drop qcs615-pcie.yaml and use sm8150, as qcs615 is the downgraded
>    version of sm8150, which can share the same yaml.
> - Drop compatible enrty in driver and use sm8150's enrty (Krzysztof)
> - Fix the DT format problem (Konrad)
> - Link to v4: https://lore.kernel.org/all/20250507031559.4085159-1-quic_ziyuzhan@quicinc.com/
>
> Changes in v4:
> - Fixed compile error found by kernel test robot(Krzysztof)
> - Update DT format (Konrad & Krzysztof)
> - Remove QCS8550 compatible use QCS615 compatible only (Konrad)
> - Update phy dt bindings to fix the dtb check errors.
> - Link to v3: https://lore.kernel.org/all/20250310065613.151598-1-quic_ziyuzhan@quicinc.com/
>
> Changes in v3:
> - Update qcs615 dt-bindings to fit the qcom-soc.yaml (Krzysztof & Dmitry)
> - Removed the driver patch and using fallback method (Mani)
> - Update DT format, keep it same with the x1e801000.dtsi (Konrad)
> - Update DT commit message (Bojor)
> - Link to v2: https://lore.kernel.org/all/20241122023314.1616353-1-quic_ziyuzhan@quicinc.com/
>
> Changes in v2:
> - Update commit message for qcs615 phy
> - Update qcs615 phy, using lowercase hex
> - Removed redundant function
> - split the soc dtsi and the platform dts into two changes
> - Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/
>
> Krishna chaitanya chundru (2):
>    arm64: dts: qcom: qcs615: enable pcie
>    arm64: dts: qcom: qcs615-ride: Enable PCIe interface
>
> Ziyue Zhang (2):
>    dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
>      for QCS615
>    dt-bindings: PCI: qcom,pcie-sm8150: document qcs615
>
>   .../bindings/pci/qcom,pcie-sm8150.yaml        |   7 +-
>   .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |   2 +-
>   arch/arm64/boot/dts/qcom/qcs615-ride.dts      |  42 +++++
>   arch/arm64/boot/dts/qcom/qcs615.dtsi          | 146 ++++++++++++++++++
>   4 files changed, 195 insertions(+), 2 deletions(-)
>
>
> base-commit: ac12494a238dba00fe8d1459fcf565f98

Hi Maintainers,

It seems merge window just close recently, can you give this series further comment ?
Thanks very much.

BRs
Ziyue

> 77960f1

On Tue, Jun 17, 2025 at 06:34:03PM +0800, Ziyue Zhang wrote:
> 
> On 5/27/2025 3:20 PM, Ziyue Zhang wrote:
> > This series adds document, phy, configs support for PCIe in QCS615.
> > 
> > This series depend on the dt-bindings change
> > https://lore.kernel.org/all/20250521-topic-8150_pcie_drop_clocks-v1-0-3d42e84f6453@oss.qualcomm.com/
> > 
> > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> > ---
> > Have following changes:
> > 	- Add a new Document the QCS615 PCIe Controller
> > 	- Add configurations in devicetree for PCIe, including registers, clocks, interrupts and phy setting sequence.
> > 	- Add configurations in devicetree for PCIe, platform related gpios, PMIC regulators, etc.
> > 
> > Changes in v5:
> > - Drop qcs615-pcie.yaml and use sm8150, as qcs615 is the downgraded
> >    version of sm8150, which can share the same yaml.
> > - Drop compatible enrty in driver and use sm8150's enrty (Krzysztof)
> > - Fix the DT format problem (Konrad)
> > - Link to v4: https://lore.kernel.org/all/20250507031559.4085159-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v4:
> > - Fixed compile error found by kernel test robot(Krzysztof)
> > - Update DT format (Konrad & Krzysztof)
> > - Remove QCS8550 compatible use QCS615 compatible only (Konrad)
> > - Update phy dt bindings to fix the dtb check errors.
> > - Link to v3: https://lore.kernel.org/all/20250310065613.151598-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v3:
> > - Update qcs615 dt-bindings to fit the qcom-soc.yaml (Krzysztof & Dmitry)
> > - Removed the driver patch and using fallback method (Mani)
> > - Update DT format, keep it same with the x1e801000.dtsi (Konrad)
> > - Update DT commit message (Bojor)
> > - Link to v2: https://lore.kernel.org/all/20241122023314.1616353-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v2:
> > - Update commit message for qcs615 phy
> > - Update qcs615 phy, using lowercase hex
> > - Removed redundant function
> > - split the soc dtsi and the platform dts into two changes
> > - Link to v1: https://lore.kernel.org/all/20241118082619.177201-1-quic_ziyuzhan@quicinc.com/
> > 
> > Krishna chaitanya chundru (2):
> >    arm64: dts: qcom: qcs615: enable pcie
> >    arm64: dts: qcom: qcs615-ride: Enable PCIe interface
> > 
> > Ziyue Zhang (2):
> >    dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
> >      for QCS615
> >    dt-bindings: PCI: qcom,pcie-sm8150: document qcs615
> > 

Applied to pci/dt-bindings, thanks!

- Mani

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