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[PATCH] arm64: dts: s32g: add RTC node

Ciprian Costea posted 1 patch 6 months, 3 weeks ago
There is a newer version of this series
arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
2 files changed, 17 insertions(+)
[PATCH] arm64: dts: s32g: add RTC node
Posted by Ciprian Costea 6 months, 3 weeks ago 
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
system suspend.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index fa054bfe7d5c..39d12422e3f3 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -114,6 +114,14 @@ soc@0 {
 		#size-cells = <1>;
 		ranges = <0 0 0 0x80000000>;
 
+		rtc0: rtc@40060000 {
+			compatible = "nxp,s32g2-rtc";
+			reg = <0x40060000 0x1000>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 54>, <&clks 55>;
+			clock-names = "ipg", "source0";
+		};
+
 		pinctrl: pinctrl@4009c240 {
 			compatible = "nxp,s32g2-siul2-pinctrl";
 				/* MSCR0-MSCR101 registers on siul2_0 */
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index b4226a9143c8..e71b80e048dc 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -171,6 +171,15 @@ soc@0 {
 		#size-cells = <1>;
 		ranges = <0 0 0 0x80000000>;
 
+		rtc0: rtc@40060000 {
+			compatible = "nxp,s32g3-rtc",
+				     "nxp,s32g2-rtc";
+			reg = <0x40060000 0x1000>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 54>, <&clks 55>;
+			clock-names = "ipg", "source0";
+		};
+
 		pinctrl: pinctrl@4009c240 {
 			compatible = "nxp,s32g2-siul2-pinctrl";
 				/* MSCR0-MSCR101 registers on siul2_0 */
-- 
2.45.2
Re: [PATCH] arm64: dts: s32g: add RTC node
Posted by Shawn Guo 6 months ago 
On Mon, May 26, 2025 at 07:21:40PM +0300, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
> system suspend.
> 
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Applied, thanks!
Re: [PATCH] arm64: dts: s32g: add RTC node
Posted by Matthias Brugger 6 months, 3 weeks ago 

On 26/05/2025 18:21, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
> system suspend.
> 
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Reviewed-by: Matthias Brugger <mbrugger@suse.com>

> ---
>   arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
>   arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
>   2 files changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index fa054bfe7d5c..39d12422e3f3 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -114,6 +114,14 @@ soc@0 {
>   		#size-cells = <1>;
>   		ranges = <0 0 0 0x80000000>;
>   
> +		rtc0: rtc@40060000 {
> +			compatible = "nxp,s32g2-rtc";
> +			reg = <0x40060000 0x1000>;
> +			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 54>, <&clks 55>;
> +			clock-names = "ipg", "source0";
> +		};
> +
>   		pinctrl: pinctrl@4009c240 {
>   			compatible = "nxp,s32g2-siul2-pinctrl";
>   				/* MSCR0-MSCR101 registers on siul2_0 */
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index b4226a9143c8..e71b80e048dc 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -171,6 +171,15 @@ soc@0 {
>   		#size-cells = <1>;
>   		ranges = <0 0 0 0x80000000>;
>   
> +		rtc0: rtc@40060000 {
> +			compatible = "nxp,s32g3-rtc",
> +				     "nxp,s32g2-rtc";
> +			reg = <0x40060000 0x1000>;
> +			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 54>, <&clks 55>;
> +			clock-names = "ipg", "source0";
> +		};
> +
>   		pinctrl: pinctrl@4009c240 {
>   			compatible = "nxp,s32g2-siul2-pinctrl";
>   				/* MSCR0-MSCR101 registers on siul2_0 */
Re: [PATCH] arm64: dts: s32g: add RTC node
Posted by Ciprian Marian Costea 6 months ago 
On 5/26/2025 9:20 PM, Matthias Brugger wrote:
> 
> 
> On 26/05/2025 18:21, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
>> system suspend.
>>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> 

Hello Shawn,

Sorry for bothering. Can you please provide feedback with respect to the 
status of this S32G2/S32G3 DTS patch ?

Regards,
Ciprian

>> ---
>>   arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
>>   arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
>>   2 files changed, 17 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/ 
>> boot/dts/freescale/s32g2.dtsi
>> index fa054bfe7d5c..39d12422e3f3 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> @@ -114,6 +114,14 @@ soc@0 {
>>           #size-cells = <1>;
>>           ranges = <0 0 0 0x80000000>;
>> +        rtc0: rtc@40060000 {
>> +            compatible = "nxp,s32g2-rtc";
>> +            reg = <0x40060000 0x1000>;
>> +            interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>> +            clocks = <&clks 54>, <&clks 55>;
>> +            clock-names = "ipg", "source0";
>> +        };
>> +
>>           pinctrl: pinctrl@4009c240 {
>>               compatible = "nxp,s32g2-siul2-pinctrl";
>>                   /* MSCR0-MSCR101 registers on siul2_0 */
>> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/ 
>> boot/dts/freescale/s32g3.dtsi
>> index b4226a9143c8..e71b80e048dc 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> @@ -171,6 +171,15 @@ soc@0 {
>>           #size-cells = <1>;
>>           ranges = <0 0 0 0x80000000>;
>> +        rtc0: rtc@40060000 {
>> +            compatible = "nxp,s32g3-rtc",
>> +                     "nxp,s32g2-rtc";
>> +            reg = <0x40060000 0x1000>;
>> +            interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>> +            clocks = <&clks 54>, <&clks 55>;
>> +            clock-names = "ipg", "source0";
>> +        };
>> +
>>           pinctrl: pinctrl@4009c240 {
>>               compatible = "nxp,s32g2-siul2-pinctrl";
>>                   /* MSCR0-MSCR101 registers on siul2_0 */

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