Add PVT DT node for thermal sensor.
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
thead,pad-group = <1>;
};
+ pvt: pvt@fffff4e000 {
+ compatible = "moortec,mr75203";
+ reg = <0xff 0xfff4e000 0x0 0x80>,
+ <0xff 0xfff4e080 0x0 0x100>,
+ <0xff 0xfff4e180 0x0 0x680>,
+ <0xff 0xfff4e800 0x0 0x600>;
+ reg-names = "common", "ts", "pd", "vm";
+ clocks = <&aonsys_clk>;
+ #thermal-sensor-cells = <1>;
+ };
+
gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
--
2.34.1On Sat, May 24, 2025 at 11:14:59PM +0200, Michal Wilczynski wrote:
> Add PVT DT node for thermal sensor.
>
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
> thead,pad-group = <1>;
> };
>
> + pvt: pvt@fffff4e000 {
> + compatible = "moortec,mr75203";
> + reg = <0xff 0xfff4e000 0x0 0x80>,
> + <0xff 0xfff4e080 0x0 0x100>,
> + <0xff 0xfff4e180 0x0 0x680>,
> + <0xff 0xfff4e800 0x0 0x600>;
> + reg-names = "common", "ts", "pd", "vm";
> + clocks = <&aonsys_clk>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> gpio@fffff52000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0xff 0xfff52000 0x0 0x1000>;
>
> --
> 2.34.1
>
I found that on my lpi4a that boot while hang after applying this patch.
I think that it is related to clocks as boot finished okay when using
clk_ignore_unused on the kernel cmdline. Do you happen have that in your
kernel cmdline?
I need to investigate further to understand which clocks are causing the
problem.
Thanks,
Drew
On 5/27/25 10:00, Drew Fustini wrote:
> On Sat, May 24, 2025 at 11:14:59PM +0200, Michal Wilczynski wrote:
>> Add PVT DT node for thermal sensor.
>>
>> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
>> ---
>> arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
>> index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
>> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
>> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
>> @@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
>> thead,pad-group = <1>;
>> };
>>
>> + pvt: pvt@fffff4e000 {
>> + compatible = "moortec,mr75203";
>> + reg = <0xff 0xfff4e000 0x0 0x80>,
>> + <0xff 0xfff4e080 0x0 0x100>,
>> + <0xff 0xfff4e180 0x0 0x680>,
>> + <0xff 0xfff4e800 0x0 0x600>;
>> + reg-names = "common", "ts", "pd", "vm";
>> + clocks = <&aonsys_clk>;
>> + #thermal-sensor-cells = <1>;
>> + };
>> +
>> gpio@fffff52000 {
>> compatible = "snps,dw-apb-gpio";
>> reg = <0xff 0xfff52000 0x0 0x1000>;
>>
>> --
>> 2.34.1
>>
>
> I found that on my lpi4a that boot while hang after applying this patch.
> I think that it is related to clocks as boot finished okay when using
> clk_ignore_unused on the kernel cmdline. Do you happen have that in your
> kernel cmdline?
>
> I need to investigate further to understand which clocks are causing the
> problem.
>
> Thanks,
> Drew
>
Thanks for your earlier message. I've investigated, and you were right
about the clocks – the specific one causing the hang is CLK_CPU2AON_X2H.
This appears to be an AHB bus clock required for CPU access to the AON
domain. My proposed solution is to make the pvt node a child of a new
parent bus node in the Device Tree. This new "AON bus" node would then
explicitly request and manage CLK_CPU2AON_X2H, ensuring it's enabled
when its children are accessed.
What are your thoughts on this approach?
Best regards,
--
Michal Wilczynski <m.wilczynski@samsung.com>
On Sun, Jun 01, 2025 at 09:50:52AM +0200, Michal Wilczynski wrote:
>
>
> On 5/27/25 10:00, Drew Fustini wrote:
> > On Sat, May 24, 2025 at 11:14:59PM +0200, Michal Wilczynski wrote:
> >> Add PVT DT node for thermal sensor.
> >>
> >> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> >> ---
> >> arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
> >> 1 file changed, 11 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> >> index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
> >> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> >> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> >> @@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
> >> thead,pad-group = <1>;
> >> };
> >>
> >> + pvt: pvt@fffff4e000 {
> >> + compatible = "moortec,mr75203";
> >> + reg = <0xff 0xfff4e000 0x0 0x80>,
> >> + <0xff 0xfff4e080 0x0 0x100>,
> >> + <0xff 0xfff4e180 0x0 0x680>,
> >> + <0xff 0xfff4e800 0x0 0x600>;
> >> + reg-names = "common", "ts", "pd", "vm";
> >> + clocks = <&aonsys_clk>;
> >> + #thermal-sensor-cells = <1>;
> >> + };
> >> +
> >> gpio@fffff52000 {
> >> compatible = "snps,dw-apb-gpio";
> >> reg = <0xff 0xfff52000 0x0 0x1000>;
> >>
> >> --
> >> 2.34.1
> >>
> >
> > I found that on my lpi4a that boot while hang after applying this patch.
> > I think that it is related to clocks as boot finished okay when using
> > clk_ignore_unused on the kernel cmdline. Do you happen have that in your
> > kernel cmdline?
> >
> > I need to investigate further to understand which clocks are causing the
> > problem.
> >
> > Thanks,
> > Drew
> >
>
> Thanks for your earlier message. I've investigated, and you were right
> about the clocks – the specific one causing the hang is CLK_CPU2AON_X2H.
Thanks for tracking down the clk causing the hang. I can confirm that
this fixes the boot hang:
diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
index ebfb1d59401d..4d0179b8c17c 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -792,7 +792,7 @@ static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_ac
0x134, BIT(8), 0);
static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd,
0x134, BIT(7), 0);
-static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), 0);
+static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), CLK_IGNORE_UNUSED);
static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd,
0x140, BIT(9), CLK_IGNORE_UNUSED);
static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd,
>
> This appears to be an AHB bus clock required for CPU access to the AON
> domain. My proposed solution is to make the pvt node a child of a new
> parent bus node in the Device Tree. This new "AON bus" node would then
> explicitly request and manage CLK_CPU2AON_X2H, ensuring it's enabled
> when its children are accessed.
>
> What are your thoughts on this approach?
I think that is a good approach. The alternative would be to just add
CLK_IGNORE_UNUSED like above. I've done it before but it is a bit of a
hack.
Thanks,
Drew
On 6/1/25 19:32, Drew Fustini wrote:
> On Sun, Jun 01, 2025 at 09:50:52AM +0200, Michal Wilczynski wrote:
>>
>>
>> On 5/27/25 10:00, Drew Fustini wrote:
>>> On Sat, May 24, 2025 at 11:14:59PM +0200, Michal Wilczynski wrote:
>>>> Add PVT DT node for thermal sensor.
>>>>
>>>> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
>>>> ---
>>>> arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
>>>> 1 file changed, 11 insertions(+)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
>>>> index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
>>>> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
>>>> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
>>>> @@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
>>>> thead,pad-group = <1>;
>>>> };
>>>>
>>>> + pvt: pvt@fffff4e000 {
>>>> + compatible = "moortec,mr75203";
>>>> + reg = <0xff 0xfff4e000 0x0 0x80>,
>>>> + <0xff 0xfff4e080 0x0 0x100>,
>>>> + <0xff 0xfff4e180 0x0 0x680>,
>>>> + <0xff 0xfff4e800 0x0 0x600>;
>>>> + reg-names = "common", "ts", "pd", "vm";
>>>> + clocks = <&aonsys_clk>;
>>>> + #thermal-sensor-cells = <1>;
>>>> + };
>>>> +
>>>> gpio@fffff52000 {
>>>> compatible = "snps,dw-apb-gpio";
>>>> reg = <0xff 0xfff52000 0x0 0x1000>;
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>> I found that on my lpi4a that boot while hang after applying this patch.
>>> I think that it is related to clocks as boot finished okay when using
>>> clk_ignore_unused on the kernel cmdline. Do you happen have that in your
>>> kernel cmdline?
>>>
>>> I need to investigate further to understand which clocks are causing the
>>> problem.
>>>
>>> Thanks,
>>> Drew
>>>
>>
>> Thanks for your earlier message. I've investigated, and you were right
>> about the clocks – the specific one causing the hang is CLK_CPU2AON_X2H.
>
> Thanks for tracking down the clk causing the hang. I can confirm that
> this fixes the boot hang:
>
> diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
> index ebfb1d59401d..4d0179b8c17c 100644
> --- a/drivers/clk/thead/clk-th1520-ap.c
> +++ b/drivers/clk/thead/clk-th1520-ap.c
> @@ -792,7 +792,7 @@ static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_ac
> 0x134, BIT(8), 0);
> static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd,
> 0x134, BIT(7), 0);
> -static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), 0);
> +static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), CLK_IGNORE_UNUSED);
> static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd,
> 0x140, BIT(9), CLK_IGNORE_UNUSED);
> static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd,
>
>>
>> This appears to be an AHB bus clock required for CPU access to the AON
>> domain. My proposed solution is to make the pvt node a child of a new
>> parent bus node in the Device Tree. This new "AON bus" node would then
>> explicitly request and manage CLK_CPU2AON_X2H, ensuring it's enabled
>> when its children are accessed.
>>
>> What are your thoughts on this approach?
>
> I think that is a good approach. The alternative would be to just add
> CLK_IGNORE_UNUSED like above. I've done it before but it is a bit of a
> hack.
I've followed up on the idea of creating a parent bus node. My attempt
using simple-pm-bus ran into a couple of significant issues that suggest
it's not the correct path.
First, the TRM doesn't seem to specify an address range for this bus.
The range I used in my test was only for the PVT controller itself,
which would be an incorrect abstraction in the device tree.
Second, simple-pm-bus requires its child nodes to use the PM runtime API
(pm_runtime_resume_and_get, etc.). Forcing this on consumer drivers like
the PVT sensor seems like an inappropriate dependency.
Additionally, I discovered that the PWM driver has a similar problem,
silently failing because another clock, CLK_PERISYS_APB1_HCLK, is not
enabled.
The most correct solution likely involves refactoring the clock parent
relationships in clk-th1520-ap.c. However, as a more immediate and less
invasive fix, I propose we apply the CLK_IGNORE_UNUSED flag for both
CLK_CPU2AON_X2H and CLK_PERISYS_APB1_HCLK in the v2 patch. This will fix
the boot hang and the PWM issue while we consider the larger clock
driver changes separately.
Does that sound like a reasonable plan for the v2 series?
>
> Thanks,
> Drew
>
Best regards,
--
Michal Wilczynski <m.wilczynski@samsung.com>
On Mon, Jun 09, 2025 at 08:49:57PM +0200, Michal Wilczynski wrote:
>
>
> On 6/1/25 19:32, Drew Fustini wrote:
> > On Sun, Jun 01, 2025 at 09:50:52AM +0200, Michal Wilczynski wrote:
> >>
> >>
> >> On 5/27/25 10:00, Drew Fustini wrote:
> >>> On Sat, May 24, 2025 at 11:14:59PM +0200, Michal Wilczynski wrote:
> >>>> Add PVT DT node for thermal sensor.
> >>>>
> >>>> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> >>>> ---
> >>>> arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
> >>>> 1 file changed, 11 insertions(+)
> >>>>
> >>>> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> >>>> index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
> >>>> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> >>>> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> >>>> @@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
> >>>> thead,pad-group = <1>;
> >>>> };
> >>>>
> >>>> + pvt: pvt@fffff4e000 {
> >>>> + compatible = "moortec,mr75203";
> >>>> + reg = <0xff 0xfff4e000 0x0 0x80>,
> >>>> + <0xff 0xfff4e080 0x0 0x100>,
> >>>> + <0xff 0xfff4e180 0x0 0x680>,
> >>>> + <0xff 0xfff4e800 0x0 0x600>;
> >>>> + reg-names = "common", "ts", "pd", "vm";
> >>>> + clocks = <&aonsys_clk>;
> >>>> + #thermal-sensor-cells = <1>;
> >>>> + };
> >>>> +
> >>>> gpio@fffff52000 {
> >>>> compatible = "snps,dw-apb-gpio";
> >>>> reg = <0xff 0xfff52000 0x0 0x1000>;
> >>>>
> >>>> --
> >>>> 2.34.1
> >>>>
> >>>
> >>> I found that on my lpi4a that boot while hang after applying this patch.
> >>> I think that it is related to clocks as boot finished okay when using
> >>> clk_ignore_unused on the kernel cmdline. Do you happen have that in your
> >>> kernel cmdline?
> >>>
> >>> I need to investigate further to understand which clocks are causing the
> >>> problem.
> >>>
> >>> Thanks,
> >>> Drew
> >>>
> >>
> >> Thanks for your earlier message. I've investigated, and you were right
> >> about the clocks – the specific one causing the hang is CLK_CPU2AON_X2H.
> >
> > Thanks for tracking down the clk causing the hang. I can confirm that
> > this fixes the boot hang:
> >
> > diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
> > index ebfb1d59401d..4d0179b8c17c 100644
> > --- a/drivers/clk/thead/clk-th1520-ap.c
> > +++ b/drivers/clk/thead/clk-th1520-ap.c
> > @@ -792,7 +792,7 @@ static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_ac
> > 0x134, BIT(8), 0);
> > static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd,
> > 0x134, BIT(7), 0);
> > -static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), 0);
> > +static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), CLK_IGNORE_UNUSED);
> > static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd,
> > 0x140, BIT(9), CLK_IGNORE_UNUSED);
> > static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd,
> >
> >>
> >> This appears to be an AHB bus clock required for CPU access to the AON
> >> domain. My proposed solution is to make the pvt node a child of a new
> >> parent bus node in the Device Tree. This new "AON bus" node would then
> >> explicitly request and manage CLK_CPU2AON_X2H, ensuring it's enabled
> >> when its children are accessed.
> >>
> >> What are your thoughts on this approach?
> >
> > I think that is a good approach. The alternative would be to just add
> > CLK_IGNORE_UNUSED like above. I've done it before but it is a bit of a
> > hack.
>
> I've followed up on the idea of creating a parent bus node. My attempt
> using simple-pm-bus ran into a couple of significant issues that suggest
> it's not the correct path.
>
> First, the TRM doesn't seem to specify an address range for this bus.
> The range I used in my test was only for the PVT controller itself,
> which would be an incorrect abstraction in the device tree.
>
> Second, simple-pm-bus requires its child nodes to use the PM runtime API
> (pm_runtime_resume_and_get, etc.). Forcing this on consumer drivers like
> the PVT sensor seems like an inappropriate dependency.
>
> Additionally, I discovered that the PWM driver has a similar problem,
> silently failing because another clock, CLK_PERISYS_APB1_HCLK, is not
> enabled.
>
> The most correct solution likely involves refactoring the clock parent
> relationships in clk-th1520-ap.c. However, as a more immediate and less
> invasive fix, I propose we apply the CLK_IGNORE_UNUSED flag for both
> CLK_CPU2AON_X2H and CLK_PERISYS_APB1_HCLK in the v2 patch. This will fix
> the boot hang and the PWM issue while we consider the larger clock
> driver changes separately.
>
> Does that sound like a reasonable plan for the v2 series?
Yes, I think that sounds like a good plan. I am okay with adding
CLK_IGNORE_UNUSED for CLK_CPU2AON_X2H and CLK_PERISYS_APB1_HCLK until a
better solution is found.
I like the idea of revisting the parent relationships in the driver. I
added CLK_IGNORE_UNUSED to several clocks in order to fix boot hangs
when I removed clk_ignore_unused from the kernel cmdline. However, I
don't think that I addressed the root cause.
Thanks,
Drew
.
W dniu 27.05.2025 o 10:00, Drew Fustini pisze:
> On Sat, May 24, 2025 at 11:14:59PM +0200, Michal Wilczynski wrote:
>> Add PVT DT node for thermal sensor.
>>
>> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
>> ---
>> arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
>> index f24e12d7259fabcfbdc2dfa966d759db06684ab4..faf5c3aaf209b24cd99ddc377a88e08a8cce24fe 100644
>> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
>> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
>> @@ -648,6 +648,17 @@ padctrl_aosys: pinctrl@fffff4a000 {
>> thead,pad-group = <1>;
>> };
>>
>> + pvt: pvt@fffff4e000 {
>> + compatible = "moortec,mr75203";
>> + reg = <0xff 0xfff4e000 0x0 0x80>,
>> + <0xff 0xfff4e080 0x0 0x100>,
>> + <0xff 0xfff4e180 0x0 0x680>,
>> + <0xff 0xfff4e800 0x0 0x600>;
>> + reg-names = "common", "ts", "pd", "vm";
>> + clocks = <&aonsys_clk>;
>> + #thermal-sensor-cells = <1>;
>> + };
>> +
>> gpio@fffff52000 {
>> compatible = "snps,dw-apb-gpio";
>> reg = <0xff 0xfff52000 0x0 0x1000>;
>>
>> --
>> 2.34.1
>>
> I found that on my lpi4a that boot while hang after applying this patch.
> I think that it is related to clocks as boot finished okay when using
> clk_ignore_unused on the kernel cmdline. Do you happen have that in your
> kernel cmdline?
Right I had that option enabled, that's why I've missed this. Thanks for
letting me know ! I'll remove this option for future testing.
>
> I need to investigate further to understand which clocks are causing the
> problem.
No problem I can look into that as well, most likely towards the end
of the week as I'm travelling and don't have access to the board.
>
> Thanks,
> Drew
>
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