Add new netlink attribute to allow user space configuration of reference
sync pin pairs, where both pins are used to provide one clock signal
consisting of both: base frequency and sync signal.
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Milena Olech <milena.olech@intel.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
v4:
- no change.
---
Documentation/driver-api/dpll.rst | 25 +++++++++++++++++++++++++
Documentation/netlink/specs/dpll.yaml | 19 +++++++++++++++++++
drivers/dpll/dpll_nl.c | 10 ++++++++--
drivers/dpll/dpll_nl.h | 1 +
include/uapi/linux/dpll.h | 1 +
5 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst
index e6855cd37e85..7570890c6cd1 100644
--- a/Documentation/driver-api/dpll.rst
+++ b/Documentation/driver-api/dpll.rst
@@ -235,6 +235,31 @@ the pin.
``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC
========================================= =================================
+Reference SYNC
+==============
+
+The device may support the Reference SYNC feature, which allows the combination
+of two inputs into a Reference SYNC pair. In this configuration, clock signals
+from both inputs are used to synchronize the dpll device. The higher frequency
+signal is utilized for the loop bandwidth of the DPLL, while the lower frequency
+signal is used to syntonize the output signal of the DPLL device. This feature
+enables the provision of a high-quality loop bandwidth signal from an external
+source.
+
+A capable input provides a list of inputs that can be paired to create a
+Reference SYNC pair. To control this feature, the user must request a desired
+state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or
+``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. Only two pins can be
+bound to form a Reference SYNC pair at any given time.
+
+ ============================== ==========================================
+ ``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or
+ requesting configuration of the Reference
+ SYNC feature
+ ``DPLL_A_PIN_ID`` target pin id for Reference SYNC pair
+ ``DPLL_A_PIN_STATE`` state of Reference SYNC pair connection
+ ============================== ==========================================
+
Configuration commands group
============================
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 8feefeae5376..333b4596b36f 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -406,6 +406,15 @@ attribute-sets:
doc: |
A ratio of high to low state of a SYNC signal pulse embedded
into base clock frequency. Value is in percents.
+ -
+ name: reference-sync
+ type: nest
+ multi-attr: true
+ nested-attributes: reference-sync
+ doc: |
+ Capable pin provides list of pins that can be bound to create a
+ reference-sync pin pair.
+
-
name: pin-parent-device
subset-of: pin
@@ -436,6 +445,14 @@ attribute-sets:
name: frequency-min
-
name: frequency-max
+ -
+ name: reference-sync
+ subset-of: pin
+ attributes:
+ -
+ name: id
+ -
+ name: state
operations:
enum-name: dpll_cmd
@@ -574,6 +591,7 @@ operations:
- esync-frequency
- esync-frequency-supported
- esync-pulse
+ - reference-sync
dump:
request:
@@ -601,6 +619,7 @@ operations:
- parent-pin
- phase-adjust
- esync-frequency
+ - reference-sync
-
name: pin-create-ntf
doc: Notification about pin appearing
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index fe9b6893d261..d709a8dc304f 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -24,6 +24,11 @@ const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
};
+const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {
+ [DPLL_A_PIN_ID] = { .type = NLA_U32, },
+ [DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
+};
+
/* DPLL_CMD_DEVICE_ID_GET - do */
static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {
[DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },
@@ -62,7 +67,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
};
/* DPLL_CMD_PIN_SET - do */
-static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY + 1] = {
+static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_REFERENCE_SYNC + 1] = {
[DPLL_A_PIN_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -72,6 +77,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY
[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
[DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
[DPLL_A_PIN_ESYNC_FREQUENCY] = { .type = NLA_U64, },
+ [DPLL_A_PIN_REFERENCE_SYNC] = NLA_POLICY_NESTED(dpll_reference_sync_nl_policy),
};
/* Ops table for dpll */
@@ -139,7 +145,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
.doit = dpll_nl_pin_set_doit,
.post_doit = dpll_pin_post_doit,
.policy = dpll_pin_set_nl_policy,
- .maxattr = DPLL_A_PIN_ESYNC_FREQUENCY,
+ .maxattr = DPLL_A_PIN_REFERENCE_SYNC,
.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
},
};
diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h
index f491262bee4f..3da10cfe9a6e 100644
--- a/drivers/dpll/dpll_nl.h
+++ b/drivers/dpll/dpll_nl.h
@@ -14,6 +14,7 @@
/* Common nested types */
extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
+extern const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1];
int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
struct genl_info *info);
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index bf97d4b6d51f..f6cb6209566c 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -237,6 +237,7 @@ enum dpll_a_pin {
DPLL_A_PIN_ESYNC_FREQUENCY,
DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
DPLL_A_PIN_ESYNC_PULSE,
+ DPLL_A_PIN_REFERENCE_SYNC,
__DPLL_A_PIN_MAX,
DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
--
2.38.1On Fri, 23 May 2025 19:26:48 +0200 Arkadiusz Kubalewski wrote: > +The device may support the Reference SYNC feature, which allows the combination > +of two inputs into a Reference SYNC pair. In this configuration, clock signals > +from both inputs are used to synchronize the dpll device. The higher frequency > +signal is utilized for the loop bandwidth of the DPLL, while the lower frequency > +signal is used to syntonize the output signal of the DPLL device. This feature > +enables the provision of a high-quality loop bandwidth signal from an external > +source. I'm uninitiated into the deeper arts of time sync, but to me this sounds like a reference clock. Are you trying not to call it clock because in time clock means a ticker, and this is an oscillator? > +A capable input provides a list of inputs that can be paired to create a > +Reference SYNC pair. To control this feature, the user must request a desired > +state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or > +``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. Only two pins can be > +bound to form a Reference SYNC pair at any given time. Mostly I got confused by the doc saying "Reference SYNC pair". I was expecting that you'll have to provide 2 ref sync signals. But IIUC the first signal is still the existing signal we lock into, so the pair is of a reference sync + an input pin? Not a pair of two reference syncs. IOW my reading of the doc made me expect 2 pins to always be passed in as ref sync, but the example from the cover letter shows only adding one.
>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of >Jakub Kicinski >Sent: Friday, May 30, 2025 2:49 AM > >On Fri, 23 May 2025 19:26:48 +0200 Arkadiusz Kubalewski wrote: >> +The device may support the Reference SYNC feature, which allows the >>combination >> +of two inputs into a Reference SYNC pair. In this configuration, clock >>signals >> +from both inputs are used to synchronize the dpll device. The higher >>frequency >> +signal is utilized for the loop bandwidth of the DPLL, while the lower >>frequency >> +signal is used to syntonize the output signal of the DPLL device. This >>feature >> +enables the provision of a high-quality loop bandwidth signal from an >>external >> +source. > >I'm uninitiated into the deeper arts of time sync, but to me this >sounds like a reference clock. Are you trying not to call it clock >because in time clock means a ticker, and this is an oscillator? > We shall refer to a reference clock for each input pin, right? TBH, I have reused the name from dpll chip docs, I believe they have tried to make similar features and naming convention for both: Embedded SYNC/Reference SYNC, and that makes some sense. >> +A capable input provides a list of inputs that can be paired to create a >> +Reference SYNC pair. To control this feature, the user must request a >>desired >> +state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or >> +``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. Only two pins >>can be >> +bound to form a Reference SYNC pair at any given time. > >Mostly I got confused by the doc saying "Reference SYNC pair". >I was expecting that you'll have to provide 2 ref sync signals. >But IIUC the first signal is still the existing signal we lock >into, so the pair is of a reference sync + an input pin? >Not a pair of two reference syncs. > >IOW my reading of the doc made me expect 2 pins to always be passed in >as ref sync, but the example from the cover letter shows only adding >one. Yes, exactly, will try to improve this in next version. Thank you! Arkadiusz
On 5/23/25 7:26 PM, Arkadiusz Kubalewski wrote: > Add new netlink attribute to allow user space configuration of reference > sync pin pairs, where both pins are used to provide one clock signal > consisting of both: base frequency and sync signal. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Reviewed-by: Milena Olech <milena.olech@intel.com> > Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Same reasoning of the other series, please repost after the merge window, thanks! Paolo
Fri, May 23, 2025 at 07:26:48PM +0200, arkadiusz.kubalewski@intel.com wrote: >Add new netlink attribute to allow user space configuration of reference >sync pin pairs, where both pins are used to provide one clock signal >consisting of both: base frequency and sync signal. > >Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> >Reviewed-by: Milena Olech <milena.olech@intel.com> >Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com>
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