The Cadence Octal SPI (OSPI) controller on AMD Versal SoCs requires only
one reset entry. To reflect this, the maxItems for "resets" and
"reset-names" has been set to 1 for AMD Versal SoCs, and the minItems for
these properties has also been updated to 1.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
---
BRANCH: mtd/next

Changes in v2:
 - Removed "resets" & "reset-names" from required properties.
 - To address review comments, removed "maxItems" from "reset-names".
---
 .../devicetree/bindings/spi/cdns,qspi-nor.yaml        | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index d48ecd6cd5ad..648b8452877c 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -17,6 +17,13 @@ allOf:
           contains:
             const: xlnx,versal-ospi-1.0
     then:
+      properties:
+        resets:
+          maxItems: 1
+
+        reset-names:
+          items:
+            enum: [ qspi ]
       required:
         - power-domains
   - if:
@@ -132,11 +139,11 @@ properties:
     maxItems: 1
 
   resets:
-    minItems: 2
+    minItems: 1
     maxItems: 3
 
   reset-names:
-    minItems: 2
+    minItems: 1
     maxItems: 3
     items:
       enum: [ qspi, qspi-ocp, rstc_ref ]
-- 
2.34.1

On Thu, May 22, 2025 at 04:17:45PM +0530, Amit Kumar Mahapatra wrote:
> The Cadence Octal SPI (OSPI) controller on AMD Versal SoCs requires only
> one reset entry. To reflect this, the maxItems for "resets" and
> "reset-names" has been set to 1 for AMD Versal SoCs, and the minItems for
> these properties has also been updated to 1.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
> BRANCH: mtd/next
> 
> Changes in v2:
>  - Removed "resets" & "reset-names" from required properties.
>  - To address review comments, removed "maxItems" from "reset-names".
> ---
>  .../devicetree/bindings/spi/cdns,qspi-nor.yaml        | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> index d48ecd6cd5ad..648b8452877c 100644
> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> @@ -17,6 +17,13 @@ allOf:
>            contains:
>              const: xlnx,versal-ospi-1.0
>      then:
> +      properties:
> +        resets:
> +          maxItems: 1
> +
> +        reset-names:
> +          items:
> +            enum: [ qspi ]
>        required:
>          - power-domains
>    - if:
> @@ -132,11 +139,11 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    minItems: 2
> +    minItems: 1

I think you're still missing one of the things Krzysztof requested on
v1, cos you reduce minItems for all platforms without restricting
it back to 2 for non-versal platforms.

>      maxItems: 3
>  
>    reset-names:
> -    minItems: 2
> +    minItems: 1
>      maxItems: 3
>      items:
>        enum: [ qspi, qspi-ocp, rstc_ref ]
> -- 
> 2.34.1
> 

On Thu, May 22, 2025 at 04:17:45PM +0530, Amit Kumar Mahapatra wrote:
> The Cadence Octal SPI (OSPI) controller on AMD Versal SoCs requires only
> one reset entry. To reflect this, the maxItems for "resets" and
> "reset-names" has been set to 1 for AMD Versal SoCs, and the minItems for
> these properties has also been updated to 1.

Acked-by: Mark Brown <broonie@kernel.org>