On Wed, May 21, 2025 at 05:09:40PM GMT, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas USB PHY hardware block receives an input signal from the system
> controller. This signal must be controlled during power-on, power-off, and
> system suspend/resume sequences as follows:
> - during power-on/resume, it must be de-asserted before enabling clocks and
> modules
> - during power-off/suspend, it must be asserted after disabling clocks and
> modules
>
> Add the renesas,sysc-signals device tree property, which allows the
> reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system
> controller signal at the appropriate time. Along with it add a new
> compatible for the RZ/G3S SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v3:
> - none; this patch is new
>
> .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 38 ++++++++++++++++---
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> index b0b20af15313..75134330f797 100644
> --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> @@ -15,12 +15,15 @@ description:
>
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
> - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
> - - const: renesas,rzg2l-usbphy-ctrl
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
> + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
> + - const: renesas,rzg2l-usbphy-ctrl
> +
Drop blank line
> + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S
>
> reg:
> maxItems: 1
> @@ -48,6 +51,16 @@ properties:
> $ref: /schemas/regulator/regulator.yaml#
> unevaluatedProperties: false
>
> + renesas,sysc-signals:
> + description: System controller phandle, specifying the register
> + offset and bitmask associated with a specific system controller signal
Same comments.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: system controller phandle
> + - description: register offset associated with a signal
> + - description: register bitmask associated with a signal
> +
> required:
> - compatible
> - reg
> @@ -57,6 +70,19 @@ required:
> - '#reset-cells'
> - regulator-vbus
Best regards,
Krzysztof