arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

[PATCH] arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

Posted by Wadim Egorov 6 months, 3 weeks ago

For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must
be supplied on CLKOUT0. Previously, our bootloader configured this
clock, which is why the PRU Ethernet ports appeared to work, but the
change never made it into the device tree.

Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index f63c101b7d61..129524eb5b91 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -322,6 +322,8 @@ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7)	/* (U21) GPMC0_AD1.GPIO0_16 */
 &icssg0_mdio {
 	pinctrl-names = "default";
 	pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
+	assigned-clocks = <&k3_clks 157 123>;
+	assigned-clock-parents = <&k3_clks 157 125>;
 	status = "okay";
 
 	icssg0_phy1: ethernet-phy@1 {
-- 
2.34.1

Re: [PATCH] arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

Posted by Vignesh Raghavendra 5 months, 3 weeks ago

Hi Wadim Egorov,

On Wed, 21 May 2025 07:33:39 +0200, Wadim Egorov wrote:
> For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must
> be supplied on CLKOUT0. Previously, our bootloader configured this
> clock, which is why the PRU Ethernet ports appeared to work, but the
> change never made it into the device tree.
> 
> Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock.
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/1] arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports
      commit: 945e48a39c957924bc84d1a6c137da039e13855b

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh

Re: [PATCH] arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

Posted by Vignesh Raghavendra 6 months, 3 weeks ago


On 21/05/25 11:03, Wadim Egorov wrote:
> For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must
> be supplied on CLKOUT0. Previously, our bootloader configured this
> clock, which is why the PRU Ethernet ports appeared to work, but the
> change never made it into the device tree.
> 

Should this patch have a Fixes tag then?

> Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock.
> 
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> ---
>  arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> index f63c101b7d61..129524eb5b91 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> @@ -322,6 +322,8 @@ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7)	/* (U21) GPMC0_AD1.GPIO0_16 */
>  &icssg0_mdio {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
> +	assigned-clocks = <&k3_clks 157 123>;
> +	assigned-clock-parents = <&k3_clks 157 125>;
>  	status = "okay";
>  
>  	icssg0_phy1: ethernet-phy@1 {

-- 
Regards
Vignesh
https://ti.com/opensource

Re: [PATCH] arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

Posted by Wadim Egorov 6 months, 3 weeks ago

Am 26.05.25 um 08:32 schrieb Vignesh Raghavendra:
> 
> 
> On 21/05/25 11:03, Wadim Egorov wrote:
>> For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must
>> be supplied on CLKOUT0. Previously, our bootloader configured this
>> clock, which is why the PRU Ethernet ports appeared to work, but the
>> change never made it into the device tree.
>>
> 
> Should this patch have a Fixes tag then?

Yes,

Fixes: 87adfd1ab03a ("arm64: dts: ti: am642-phyboard-electra: Add 
PRU-ICSSG nodes")

> 
>> Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock.
>>
>> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
>> ---
>>   arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
>> index f63c101b7d61..129524eb5b91 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
>> @@ -322,6 +322,8 @@ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7)	/* (U21) GPMC0_AD1.GPIO0_16 */
>>   &icssg0_mdio {
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
>> +	assigned-clocks = <&k3_clks 157 123>;
>> +	assigned-clock-parents = <&k3_clks 157 125>;
>>   	status = "okay";
>>   
>>   	icssg0_phy1: ethernet-phy@1 {
>