From: Rik van Riel <riel@fb.com>
Introduce X86_FEATURE_RAR and enumeration of the feature.
[riel: moved initialization to intel.c and disabling to Kconfig.cpufeatures]
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rik van Riel <riel@surriel.com>
---
arch/x86/Kconfig.cpufeatures | 4 ++++
arch/x86/include/asm/cpufeatures.h | 2 +-
arch/x86/kernel/cpu/common.c | 13 +++++++++++++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
index 250c10627ab3..7d459b5f47f7 100644
--- a/arch/x86/Kconfig.cpufeatures
+++ b/arch/x86/Kconfig.cpufeatures
@@ -195,3 +195,7 @@ config X86_DISABLED_FEATURE_SEV_SNP
config X86_DISABLED_FEATURE_INVLPGB
def_bool y
depends on !BROADCAST_TLB_FLUSH
+
+config X86_DISABLED_FEATURE_RAR
+ def_bool y
+ depends on !BROADCAST_TLB_FLUSH
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 5b50e0e35129..0729c2d54109 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -76,7 +76,7 @@
#define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */
#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
#define X86_FEATURE_ZEN6 ( 3*32+ 6) /* CPU based on Zen6 microarchitecture */
-/* Free ( 3*32+ 7) */
+#define X86_FEATURE_RAR ( 3*32+ 7) /* Intel Remote Action Request */
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at a constant rate */
#define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */
#define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8feb8fd2957a..dd662c42f510 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1545,6 +1545,18 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
setup_force_cpu_bug(X86_BUG_L1TF);
}
+static void __init detect_rar(struct cpuinfo_x86 *c)
+{
+ u64 msr;
+
+ if (cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) {
+ rdmsrl(MSR_IA32_CORE_CAPABILITIES, msr);
+
+ if (msr & CORE_CAP_RAR)
+ setup_force_cpu_cap(X86_FEATURE_RAR);
+ }
+}
+
/*
* The NOPL instruction is supposed to exist on all CPUs of family >= 6;
* unfortunately, that's not true in practice because of early VIA
@@ -1771,6 +1783,7 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
setup_clear_cpu_cap(X86_FEATURE_LA57);
detect_nopl();
+ detect_rar(c);
}
void __init init_cpu_devs(void)
--
2.49.0On Mon, May 19, 2025 at 09:02:29PM -0400, Rik van Riel wrote:
> From: Rik van Riel <riel@fb.com>
>
> Introduce X86_FEATURE_RAR and enumeration of the feature.
>
> [riel: moved initialization to intel.c and disabling to Kconfig.cpufeatures]
>
> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
I'm guessing Yu-cheng is the original author - that's expressed differently.
> Signed-off-by: Rik van Riel <riel@surriel.com>
> ---
> arch/x86/Kconfig.cpufeatures | 4 ++++
> arch/x86/include/asm/cpufeatures.h | 2 +-
> arch/x86/kernel/cpu/common.c | 13 +++++++++++++
> 3 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
> index 250c10627ab3..7d459b5f47f7 100644
> --- a/arch/x86/Kconfig.cpufeatures
> +++ b/arch/x86/Kconfig.cpufeatures
> @@ -195,3 +195,7 @@ config X86_DISABLED_FEATURE_SEV_SNP
> config X86_DISABLED_FEATURE_INVLPGB
> def_bool y
> depends on !BROADCAST_TLB_FLUSH
> +
> +config X86_DISABLED_FEATURE_RAR
> + def_bool y
> + depends on !BROADCAST_TLB_FLUSH
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 5b50e0e35129..0729c2d54109 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -76,7 +76,7 @@
> #define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */
> #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
> #define X86_FEATURE_ZEN6 ( 3*32+ 6) /* CPU based on Zen6 microarchitecture */
> -/* Free ( 3*32+ 7) */
> +#define X86_FEATURE_RAR ( 3*32+ 7) /* Intel Remote Action Request */
> #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at a constant rate */
> #define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */
> #define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 8feb8fd2957a..dd662c42f510 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -1545,6 +1545,18 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
> setup_force_cpu_bug(X86_BUG_L1TF);
> }
>
> +static void __init detect_rar(struct cpuinfo_x86 *c)
> +{
> + u64 msr;
> +
> + if (cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) {
> + rdmsrl(MSR_IA32_CORE_CAPABILITIES, msr);
> +
> + if (msr & CORE_CAP_RAR)
> + setup_force_cpu_cap(X86_FEATURE_RAR);
> + }
> +}
> +
> /*
> * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
> * unfortunately, that's not true in practice because of early VIA
> @@ -1771,6 +1783,7 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
> setup_clear_cpu_cap(X86_FEATURE_LA57);
>
> detect_nopl();
> + detect_rar(c);
> }
Move all this gunk into early_init_intel().
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On Wed, 2025-05-21 at 13:53 +0200, Borislav Petkov wrote: > On Mon, May 19, 2025 at 09:02:29PM -0400, Rik van Riel wrote: > > From: Rik van Riel <riel@fb.com> > > > > Introduce X86_FEATURE_RAR and enumeration of the feature. > > > > [riel: moved initialization to intel.c and disabling to > > Kconfig.cpufeatures] > > > > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> > > I'm guessing Yu-cheng is the original author - that's expressed > differently. I will fix that up! > > > @@ -1771,6 +1783,7 @@ static void __init early_identify_cpu(struct > > cpuinfo_x86 *c) > > setup_clear_cpu_cap(X86_FEATURE_LA57); > > > > detect_nopl(); > > + detect_rar(c); > > } > > Move all this gunk into early_init_intel(). > I had the same thought, and tried that already. It didn't work. -- All Rights Reversed.
On Wed, May 21, 2025 at 09:57:52AM -0400, Rik van Riel wrote:
> I had the same thought, and tried that already.
>
> It didn't work.
Care to share why?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On Wed, 2025-05-21 at 16:53 +0200, Borislav Petkov wrote: > On Wed, May 21, 2025 at 09:57:52AM -0400, Rik van Riel wrote: > > I had the same thought, and tried that already. > > > > It didn't work. > > Care to share why? > It resulted in RAR not being properly initialized, and the system hanging when trying to use RAR to flush the TLB. I don't remember exactly what sequence of events was happening here, maybe something with the boot CPU per-cpu RAR initialization being called (or not, due to X86_FEATURE_RAR not being set) before the systemwide initialization? -- All Rights Reversed.
On Wed, May 21, 2025 at 12:06:59PM -0400, Rik van Riel wrote:
> On Wed, 2025-05-21 at 16:53 +0200, Borislav Petkov wrote:
> > On Wed, May 21, 2025 at 09:57:52AM -0400, Rik van Riel wrote:
> > > I had the same thought, and tried that already.
> > >
> > > It didn't work.
> >
> > Care to share why?
> >
> It resulted in RAR not being properly initialized,
> and the system hanging when trying to use RAR to
> flush the TLB.
>
> I don't remember exactly what sequence of events
> was happening here, maybe something with the
> boot CPU per-cpu RAR initialization being called
> (or not, due to X86_FEATURE_RAR not being set)
> before the systemwide initialization?
I'm asking you to move it from this path to
if (this_cpu->c_early_init)
this_cpu->c_early_init(c);
or
if (this_cpu->c_bsp_init)
this_cpu->c_bsp_init(c);
a couple of lines above.
This doesn't change anything: you're still running it on the BSP once. So
I don't see how any of the above confusion would happen.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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