[v2] Intel RAR TLB invalidation

[RFC v2 1/9] x86/mm: Introduce MSR_IA32_CORE_CAPABILITIES

Posted by Rik van Riel 6 months, 4 weeks ago

From: Yu-cheng Yu <yu-cheng.yu@intel.com>

MSR_IA32_CORE_CAPABILITIES indicates the existence of other MSRs.
Bit[1] indicates Remote Action Request (RAR) TLB registers.

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rik van Riel <riel@surriel.com>
---
 arch/x86/include/asm/msr-index.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3c8113..c848dd4bfceb 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -220,6 +220,12 @@
 						     * their affected status.
 						     */
 
+#define MSR_IA32_CORE_CAPABILITIES	0x000000cf
+#define CORE_CAP_RAR			BIT(1)	/*
+						 * Remote Action Request. Used to directly
+						 * flush the TLB on remote CPUs.
+						 */
+
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
 						 * Writeback and invalidate the
-- 
2.49.0

Re: [RFC v2 1/9] x86/mm: Introduce MSR_IA32_CORE_CAPABILITIES

Posted by Sean Christopherson 6 months, 3 weeks ago

On Mon, May 19, 2025, Rik van Riel wrote:
> From: Yu-cheng Yu <yu-cheng.yu@intel.com>
> 
> MSR_IA32_CORE_CAPABILITIES indicates the existence of other MSRs.
> Bit[1] indicates Remote Action Request (RAR) TLB registers.
> 
> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
> Signed-off-by: Rik van Riel <riel@surriel.com>
> ---
>  arch/x86/include/asm/msr-index.h | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index b7dded3c8113..c848dd4bfceb 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -220,6 +220,12 @@
>  						     * their affected status.
>  						     */
>  
> +#define MSR_IA32_CORE_CAPABILITIES	0x000000cf
> +#define CORE_CAP_RAR			BIT(1)	/*
> +						 * Remote Action Request. Used to directly
> +						 * flush the TLB on remote CPUs.
> +						 */

CORE_CAPABILITIES is already supported and enumerated, it's just abbreviated:

/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
#define MSR_IA32_CORE_CAPS			  0x000000cf
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT	  2
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS	  BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT	  BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)

Re: [RFC v2 1/9] x86/mm: Introduce MSR_IA32_CORE_CAPABILITIES

Posted by Dave Hansen 6 months, 4 weeks ago

On 5/19/25 18:02, Rik van Riel wrote:
> MSR_IA32_CORE_CAPABILITIES indicates the existence of other MSRs.
> Bit[1] indicates Remote Action Request (RAR) TLB registers.

Nit: This may have changed from when Yu-cheng wrote the changelog, but
RAR can do more than just flush the TLB. This probably needs to get a
refresh.