Add the bindings for the Neural Processing Unit IP from Rockchip.
v2:
- Adapt to new node structure (one node per core, each with its own
IOMMU)
- Several misc. fixes from Sebastian Reichel
v3:
- Split register block in its constituent subblocks, and only require
the ones that the kernel would ever use (Nicolas Frattaroli)
- Group supplies (Rob Herring)
- Explain the way in which the top core is special (Rob Herring)
v4:
- Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski)
- Remove unneeded items: (Krzysztof Kozlowski)
- Fix use of minItems/maxItems (Krzysztof Kozlowski)
- Add reg-names to list of required properties (Krzysztof Kozlowski)
- Fix example (Krzysztof Kozlowski)
v5:
- Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski)
- Streamline compatible property (Krzysztof Kozlowski)
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
.../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86
--- /dev/null
+++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Neural Processing Unit IP from Rockchip
+
+maintainers:
+ - Tomeu Vizoso <tomeu@tomeuvizoso.net>
+
+description:
+ Rockchip IP for accelerating inference of neural networks, based on NVIDIA's
+ open source NVDLA IP.
+
+ There is to be a node per each core in the NPU. In Rockchip's design there
+ will be one core that is special and needs to be powered on before any of the
+ other cores can be used. This special core is called the top core and should
+ have the compatible string that corresponds to top cores.
+
+properties:
+ $nodename:
+ pattern: '^npu@[a-f0-9]+$'
+
+ compatible:
+ enum:
+ - rockchip,rk3588-rknn-core-top
+ - rockchip,rk3588-rknn-core
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: pc
+ - const: cna
+ - const: core
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: hclk
+ - const: npu
+ - const: pclk
+ minItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ npu-supply: true
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: srst_a
+ - const: srst_h
+
+ sram-supply: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - iommus
+ - power-domains
+ - resets
+ - reset-names
+ - npu-supply
+ - sram-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rknn-core-top
+ then:
+ properties:
+ clocks:
+ minItems: 4
+
+ clock-names:
+ minItems: 4
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rknn-core
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ npu@fdab0000 {
+ compatible = "rockchip,rk3588-rknn-core-top";
+ reg = <0x0 0xfdab0000 0x0 0x1000>,
+ <0x0 0xfdab1000 0x0 0x1000>,
+ <0x0 0xfdab3000 0x0 0x1000>;
+ reg-names = "pc", "cna", "core";
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "aclk", "hclk", "npu", "pclk";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&rknn_mmu_top>;
+ npu-supply = <&vdd_npu_s0>;
+ power-domains = <&power RK3588_PD_NPUTOP>;
+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
+ reset-names = "srst_a", "srst_h";
+ sram-supply = <&vdd_npu_mem_s0>;
+ };
+ };
+...
--
2.49.0On Tue, May 20, 2025 at 5:27 AM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote: > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > v2: > - Adapt to new node structure (one node per core, each with its own > IOMMU) > - Several misc. fixes from Sebastian Reichel > > v3: > - Split register block in its constituent subblocks, and only require > the ones that the kernel would ever use (Nicolas Frattaroli) > - Group supplies (Rob Herring) > - Explain the way in which the top core is special (Rob Herring) > > v4: > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > - Remove unneeded items: (Krzysztof Kozlowski) > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > - Add reg-names to list of required properties (Krzysztof Kozlowski) > - Fix example (Krzysztof Kozlowski) > > v5: > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > - Streamline compatible property (Krzysztof Kozlowski) > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> > --- > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++++++++++++ > 1 file changed, 147 insertions(+) > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86 > --- /dev/null > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > @@ -0,0 +1,147 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Neural Processing Unit IP from Rockchip > + > +maintainers: > + - Tomeu Vizoso <tomeu@tomeuvizoso.net> > + > +description: > + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's > + open source NVDLA IP. > + > + There is to be a node per each core in the NPU. In Rockchip's design there > + will be one core that is special and needs to be powered on before any of the > + other cores can be used. This special core is called the top core and should > + have the compatible string that corresponds to top cores. Is this really a distinction in the h/w? If you change which core is the top one in the DT, does it still work? > + > +properties: > + $nodename: > + pattern: '^npu@[a-f0-9]+$' > + > + compatible: > + enum: > + - rockchip,rk3588-rknn-core-top > + - rockchip,rk3588-rknn-core > + > + reg: > + maxItems: 3 > + > + reg-names: > + items: > + - const: pc > + - const: cna > + - const: core > + > + clocks: > + minItems: 2 > + maxItems: 4 > + > + clock-names: > + items: > + - const: aclk > + - const: hclk > + - const: npu > + - const: pclk > + minItems: 2 It is odd that the non-top cores only have bus clocks and no module clock. But based on the clock names, I'm guessing the aclk/hclk are not shared, but the npu and pclk are shared. Since you make the top core probe first, then it will enable the shared clocks and the non-top cores don't have to worry about them. If so, that is wrong as it is letting the software design define the bindings. Rob
On Wed, May 28, 2025 at 3:41 PM Rob Herring <robh@kernel.org> wrote: > > On Tue, May 20, 2025 at 5:27 AM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote: > > > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > v2: > > - Adapt to new node structure (one node per core, each with its own > > IOMMU) > > - Several misc. fixes from Sebastian Reichel > > > > v3: > > - Split register block in its constituent subblocks, and only require > > the ones that the kernel would ever use (Nicolas Frattaroli) > > - Group supplies (Rob Herring) > > - Explain the way in which the top core is special (Rob Herring) > > > > v4: > > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > > - Remove unneeded items: (Krzysztof Kozlowski) > > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > > - Add reg-names to list of required properties (Krzysztof Kozlowski) > > - Fix example (Krzysztof Kozlowski) > > > > v5: > > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > > - Streamline compatible property (Krzysztof Kozlowski) > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> > > --- > > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++++++++++++ > > 1 file changed, 147 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > @@ -0,0 +1,147 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Neural Processing Unit IP from Rockchip > > + > > +maintainers: > > + - Tomeu Vizoso <tomeu@tomeuvizoso.net> > > + > > +description: > > + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's > > + open source NVDLA IP. > > + > > + There is to be a node per each core in the NPU. In Rockchip's design there > > + will be one core that is special and needs to be powered on before any of the > > + other cores can be used. This special core is called the top core and should > > + have the compatible string that corresponds to top cores. > > Is this really a distinction in the h/w? If you change which core is > the top one in the DT, does it still work? I asked Kever about it, and he confirmed that the core 0/top is special in that it is able to relay register writes and share data with the other cores. Regards, Tomeu > > + > > +properties: > > + $nodename: > > + pattern: '^npu@[a-f0-9]+$' > > + > > + compatible: > > + enum: > > + - rockchip,rk3588-rknn-core-top > > + - rockchip,rk3588-rknn-core > > + > > + reg: > > + maxItems: 3 > > + > > + reg-names: > > + items: > > + - const: pc > > + - const: cna > > + - const: core > > + > > + clocks: > > + minItems: 2 > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aclk > > + - const: hclk > > + - const: npu > > + - const: pclk > > + minItems: 2 > > It is odd that the non-top cores only have bus clocks and no module > clock. But based on the clock names, I'm guessing the aclk/hclk are > not shared, but the npu and pclk are shared. Since you make the top > core probe first, then it will enable the shared clocks and the > non-top cores don't have to worry about them. If so, that is wrong as > it is letting the software design define the bindings. > > Rob
Hi Rob, [adding Kever to CC] On Wed, May 28, 2025 at 3:41 PM Rob Herring <robh@kernel.org> wrote: > > On Tue, May 20, 2025 at 5:27 AM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote: > > > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > v2: > > - Adapt to new node structure (one node per core, each with its own > > IOMMU) > > - Several misc. fixes from Sebastian Reichel > > > > v3: > > - Split register block in its constituent subblocks, and only require > > the ones that the kernel would ever use (Nicolas Frattaroli) > > - Group supplies (Rob Herring) > > - Explain the way in which the top core is special (Rob Herring) > > > > v4: > > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > > - Remove unneeded items: (Krzysztof Kozlowski) > > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > > - Add reg-names to list of required properties (Krzysztof Kozlowski) > > - Fix example (Krzysztof Kozlowski) > > > > v5: > > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > > - Streamline compatible property (Krzysztof Kozlowski) > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> > > --- > > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++++++++++++ > > 1 file changed, 147 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > @@ -0,0 +1,147 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Neural Processing Unit IP from Rockchip > > + > > +maintainers: > > + - Tomeu Vizoso <tomeu@tomeuvizoso.net> > > + > > +description: > > + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's > > + open source NVDLA IP. > > + > > + There is to be a node per each core in the NPU. In Rockchip's design there > > + will be one core that is special and needs to be powered on before any of the > > + other cores can be used. This special core is called the top core and should > > + have the compatible string that corresponds to top cores. > > Is this really a distinction in the h/w? If you change which core is > the top one in the DT, does it still work? > > > + > > +properties: > > + $nodename: > > + pattern: '^npu@[a-f0-9]+$' > > + > > + compatible: > > + enum: > > + - rockchip,rk3588-rknn-core-top > > + - rockchip,rk3588-rknn-core > > + > > + reg: > > + maxItems: 3 > > + > > + reg-names: > > + items: > > + - const: pc > > + - const: cna > > + - const: core > > + > > + clocks: > > + minItems: 2 > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aclk > > + - const: hclk > > + - const: npu > > + - const: pclk > > + minItems: 2 > > It is odd that the non-top cores only have bus clocks and no module > clock. I'm not sure I get what you mean by module clock, but the TRM says this: "36.5.2 Clock and Reset 1.5.2.1 Clock Domains RKNN has two clock domains, one is AHB clock, the other is AXI clock. AHB clock, which is the clock for AHB interface, while AXI clock, which is the clock for AXI interface. AXI clock also used for core clock for every Calculate Core and Control Core. Clock frequency can be controlled by CRU, please refer to the relevant sections. Automatic localized clock gating is employed throughout the design in order to minimize the dynamic power consumption. Almost all of the flip-flops are clock gated in the design. Block level clock gating also implemented in every separate block. If a block and the interface to the block are both idle, then the clock of that block will be gated automatically. This feature can be disabled by software." So maybe the AXI (aclk?) clock is being used as what you called the module clock? > But based on the clock names, I'm guessing the aclk/hclk are > not shared, but the npu and pclk are shared. Since you make the top > core probe first, then it will enable the shared clocks and the > non-top cores don't have to worry about them. If so, that is wrong as > it is letting the software design define the bindings. I don't really know what the pclk and npu clk are needed for, but in the TRM I'm seeing references to the pclk being related to the core 0 (TOP): pclk_nputop_root_sel pclk_nputop_biu_en Couldn't find similar references to the "npu" clock though. Cheers, Tomeu
On Wed, May 28, 2025 at 3:41 PM Rob Herring <robh@kernel.org> wrote: > > On Tue, May 20, 2025 at 5:27 AM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote: > > > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > v2: > > - Adapt to new node structure (one node per core, each with its own > > IOMMU) > > - Several misc. fixes from Sebastian Reichel > > > > v3: > > - Split register block in its constituent subblocks, and only require > > the ones that the kernel would ever use (Nicolas Frattaroli) > > - Group supplies (Rob Herring) > > - Explain the way in which the top core is special (Rob Herring) > > > > v4: > > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > > - Remove unneeded items: (Krzysztof Kozlowski) > > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > > - Add reg-names to list of required properties (Krzysztof Kozlowski) > > - Fix example (Krzysztof Kozlowski) > > > > v5: > > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > > - Streamline compatible property (Krzysztof Kozlowski) > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> > > --- > > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++++++++++++ > > 1 file changed, 147 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > @@ -0,0 +1,147 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Neural Processing Unit IP from Rockchip > > + > > +maintainers: > > + - Tomeu Vizoso <tomeu@tomeuvizoso.net> > > + > > +description: > > + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's > > + open source NVDLA IP. > > + > > + There is to be a node per each core in the NPU. In Rockchip's design there > > + will be one core that is special and needs to be powered on before any of the > > + other cores can be used. This special core is called the top core and should > > + have the compatible string that corresponds to top cores. > > Is this really a distinction in the h/w? If you change which core is > the top one in the DT, does it still work? No, I really need to power on that one before the others can work (the first core is also marked as special in a diagram in the TRM). > > + > > +properties: > > + $nodename: > > + pattern: '^npu@[a-f0-9]+$' > > + > > + compatible: > > + enum: > > + - rockchip,rk3588-rknn-core-top > > + - rockchip,rk3588-rknn-core > > + > > + reg: > > + maxItems: 3 > > + > > + reg-names: > > + items: > > + - const: pc > > + - const: cna > > + - const: core > > + > > + clocks: > > + minItems: 2 > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aclk > > + - const: hclk > > + - const: npu > > + - const: pclk > > + minItems: 2 > > It is odd that the non-top cores only have bus clocks and no module > clock. But based on the clock names, I'm guessing the aclk/hclk are > not shared, but the npu and pclk are shared. Since you make the top > core probe first, then it will enable the shared clocks and the > non-top cores don't have to worry about them. If so, that is wrong as > it is letting the software design define the bindings. Yes, I think it's probably as you say, but I don't know how I could check. Maybe Kever, Heiko or Sebastian would have any ideas? Thanks, Tomeu
On Wed, May 28, 2025 at 5:34 PM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote: > > On Wed, May 28, 2025 at 3:41 PM Rob Herring <robh@kernel.org> wrote: > > > > On Tue, May 20, 2025 at 5:27 AM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote: > > > > > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > > > v2: > > > - Adapt to new node structure (one node per core, each with its own > > > IOMMU) > > > - Several misc. fixes from Sebastian Reichel > > > > > > v3: > > > - Split register block in its constituent subblocks, and only require > > > the ones that the kernel would ever use (Nicolas Frattaroli) > > > - Group supplies (Rob Herring) > > > - Explain the way in which the top core is special (Rob Herring) > > > > > > v4: > > > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > > > - Remove unneeded items: (Krzysztof Kozlowski) > > > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > > > - Add reg-names to list of required properties (Krzysztof Kozlowski) > > > - Fix example (Krzysztof Kozlowski) > > > > > > v5: > > > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > > > - Streamline compatible property (Krzysztof Kozlowski) > > > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > > Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> > > > --- > > > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++++++++++++ > > > 1 file changed, 147 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > > new file mode 100644 > > > index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d43c4b8250cdd1b9ee86 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml > > > @@ -0,0 +1,147 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Neural Processing Unit IP from Rockchip > > > + > > > +maintainers: > > > + - Tomeu Vizoso <tomeu@tomeuvizoso.net> > > > + > > > +description: > > > + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's > > > + open source NVDLA IP. > > > + > > > + There is to be a node per each core in the NPU. In Rockchip's design there > > > + will be one core that is special and needs to be powered on before any of the > > > + other cores can be used. This special core is called the top core and should > > > + have the compatible string that corresponds to top cores. > > > > Is this really a distinction in the h/w? If you change which core is > > the top one in the DT, does it still work? > > No, I really need to power on that one before the others can work (the > first core is also marked as special in a diagram in the TRM). > > > > + > > > +properties: > > > + $nodename: > > > + pattern: '^npu@[a-f0-9]+$' > > > + > > > + compatible: > > > + enum: > > > + - rockchip,rk3588-rknn-core-top > > > + - rockchip,rk3588-rknn-core > > > + > > > + reg: > > > + maxItems: 3 > > > + > > > + reg-names: > > > + items: > > > + - const: pc > > > + - const: cna > > > + - const: core > > > + > > > + clocks: > > > + minItems: 2 > > > + maxItems: 4 > > > + > > > + clock-names: > > > + items: > > > + - const: aclk > > > + - const: hclk > > > + - const: npu > > > + - const: pclk > > > + minItems: 2 > > > > It is odd that the non-top cores only have bus clocks and no module > > clock. But based on the clock names, I'm guessing the aclk/hclk are > > not shared, but the npu and pclk are shared. Since you make the top > > core probe first, then it will enable the shared clocks and the > > non-top cores don't have to worry about them. If so, that is wrong as > > it is letting the software design define the bindings. > > Yes, I think it's probably as you say, but I don't know how I could > check. Maybe Kever, Heiko or Sebastian would have any ideas? So I talked with Kever and Heiko about this, and the npu and pclk clocks are indeed shared among cores. Regards, Tomeu
On Tue, May 20, 2025 at 12:26:54PM GMT, Tomeu Vizoso wrote: > Add the bindings for the Neural Processing Unit IP from Rockchip. > > v2: > - Adapt to new node structure (one node per core, each with its own > IOMMU) > - Several misc. fixes from Sebastian Reichel > > v3: > - Split register block in its constituent subblocks, and only require > the ones that the kernel would ever use (Nicolas Frattaroli) > - Group supplies (Rob Herring) > - Explain the way in which the top core is special (Rob Herring) > > v4: > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) > - Remove unneeded items: (Krzysztof Kozlowski) > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > - Add reg-names to list of required properties (Krzysztof Kozlowski) > - Fix example (Krzysztof Kozlowski) > > v5: > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > - Streamline compatible property (Krzysztof Kozlowski) > This is a big patchset, so please slow down and do not send it every day but allow people to actually review the version you post. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
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