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[PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag

Elena Reshetova posted 5 patches 7 months ago
There is a newer version of this series
[PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag
Posted by Elena Reshetova 7 months ago 
Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction
is supported. This will be used by SGX driver to perform CPU
SVN updates.

Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
---
 arch/x86/include/asm/cpufeatures.h       | 1 +
 arch/x86/kernel/cpu/scattered.c          | 1 +
 tools/arch/x86/include/asm/cpufeatures.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6c2c152d8a67..ed0c0fa5822a 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -481,6 +481,7 @@
 #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
 #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
 #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
+#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for ENCLS[EUPDATESVN] instruction */
 
 /*
  * BUG word(s)
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 16f3ca30626a..a7e1fcedca3c 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0, 0x00000010, 3 },
 	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0 },
 	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0 },
+	{ X86_FEATURE_SGX_EUPDATESVN,	CPUID_EAX, 10, 0x00000012, 0 },
 	{ X86_FEATURE_SGX_EDECCSSA,		CPUID_EAX, 11, 0x00000012, 0 },
 	{ X86_FEATURE_HW_PSTATE,		CPUID_EDX,  7, 0x80000007, 0 },
 	{ X86_FEATURE_CPB,			CPUID_EDX,  9, 0x80000007, 0 },
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 6c2c152d8a67..ed0c0fa5822a 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -481,6 +481,7 @@
 #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
 #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
 #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
+#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for ENCLS[EUPDATESVN] instruction */
 
 /*
  * BUG word(s)
-- 
2.45.2
Re: [PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag
Posted by Huang, Kai 7 months ago 
On Mon, 2025-05-19 at 10:24 +0300, Elena Reshetova wrote:
> Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction
> is supported. This will be used by SGX driver to perform CPU
> SVN updates.
> 
> Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h       | 1 +
>  arch/x86/kernel/cpu/scattered.c          | 1 +
>  tools/arch/x86/include/asm/cpufeatures.h | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 6c2c152d8a67..ed0c0fa5822a 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -481,6 +481,7 @@
>  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
>  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
>  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for ENCLS[EUPDATESVN] instruction */
>  
>  /*
>   * BUG word(s)
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index 16f3ca30626a..a7e1fcedca3c 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = {
>  	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0, 0x00000010, 3 },
>  	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0 },
>  	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0 },
> +	{ X86_FEATURE_SGX_EUPDATESVN,	CPUID_EAX, 10, 0x00000012, 0 },
>  	{ X86_FEATURE_SGX_EDECCSSA,		CPUID_EAX, 11, 0x00000012, 0 },
>  	{ X86_FEATURE_HW_PSTATE,		CPUID_EDX,  7, 0x80000007, 0 },
>  	{ X86_FEATURE_CPB,			CPUID_EDX,  9, 0x80000007, 0 },
> diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
> index 6c2c152d8a67..ed0c0fa5822a 100644
> --- a/tools/arch/x86/include/asm/cpufeatures.h
> +++ b/tools/arch/x86/include/asm/cpufeatures.h
> @@ -481,6 +481,7 @@
>  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
>  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
>  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for ENCLS[EUPDATESVN] instruction */
>  
> 


Additionally, the new feature bit should be added to the CPUID dependency table:

--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -78,6 +78,7 @@ static const struct cpuid_dep cpuid_deps[] = {
        { X86_FEATURE_SGX_LC,                   X86_FEATURE_SGX       },
        { X86_FEATURE_SGX1,                     X86_FEATURE_SGX       },
        { X86_FEATURE_SGX2,                     X86_FEATURE_SGX1      },
+       { X86_FEATURE_SGX_EUPDATESVN,           X86_FEATURE_SGX1      },
        { X86_FEATURE_SGX_EDECCSSA,             X86_FEATURE_SGX1      },
        { X86_FEATURE_XFD,                      X86_FEATURE_XSAVES    },
        { X86_FEATURE_XFD,                      X86_FEATURE_XGETBV1   },
RE: [PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag
Posted by Reshetova, Elena 7 months ago 
 
> On Mon, 2025-05-19 at 10:24 +0300, Elena Reshetova wrote:
> > Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction
> > is supported. This will be used by SGX driver to perform CPU
> > SVN updates.
> >
> > Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
> > ---
> >  arch/x86/include/asm/cpufeatures.h       | 1 +
> >  arch/x86/kernel/cpu/scattered.c          | 1 +
> >  tools/arch/x86/include/asm/cpufeatures.h | 1 +
> >  3 files changed, 3 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> > index 6c2c152d8a67..ed0c0fa5822a 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -481,6 +481,7 @@
> >  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /*
> Heterogeneous Core Topology */
> >  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /*
> Workload Classification */
> >  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM
> registers due to downclocking */
> > +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for
> ENCLS[EUPDATESVN] instruction */
> >
> >  /*
> >   * BUG word(s)
> > diff --git a/arch/x86/kernel/cpu/scattered.c
> b/arch/x86/kernel/cpu/scattered.c
> > index 16f3ca30626a..a7e1fcedca3c 100644
> > --- a/arch/x86/kernel/cpu/scattered.c
> > +++ b/arch/x86/kernel/cpu/scattered.c
> > @@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = {
> >  	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0,
> 0x00000010, 3 },
> >  	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0
> },
> >  	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0
> },
> > +	{ X86_FEATURE_SGX_EUPDATESVN,	CPUID_EAX, 10, 0x00000012,
> 0 },
> >  	{ X86_FEATURE_SGX_EDECCSSA,		CPUID_EAX, 11,
> 0x00000012, 0 },
> >  	{ X86_FEATURE_HW_PSTATE,		CPUID_EDX,  7, 0x80000007, 0
> },
> >  	{ X86_FEATURE_CPB,			CPUID_EDX,  9, 0x80000007, 0
> },
> > diff --git a/tools/arch/x86/include/asm/cpufeatures.h
> b/tools/arch/x86/include/asm/cpufeatures.h
> > index 6c2c152d8a67..ed0c0fa5822a 100644
> > --- a/tools/arch/x86/include/asm/cpufeatures.h
> > +++ b/tools/arch/x86/include/asm/cpufeatures.h
> > @@ -481,6 +481,7 @@
> >  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /*
> Heterogeneous Core Topology */
> >  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /*
> Workload Classification */
> >  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM
> registers due to downclocking */
> > +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for
> ENCLS[EUPDATESVN] instruction */
> >
> >
> 
> 
> Additionally, the new feature bit should be added to the CPUID dependency
> table:
> 
> --- a/arch/x86/kernel/cpu/cpuid-deps.c
> +++ b/arch/x86/kernel/cpu/cpuid-deps.c
> @@ -78,6 +78,7 @@ static const struct cpuid_dep cpuid_deps[] = {
>         { X86_FEATURE_SGX_LC,                   X86_FEATURE_SGX       },
>         { X86_FEATURE_SGX1,                     X86_FEATURE_SGX       },
>         { X86_FEATURE_SGX2,                     X86_FEATURE_SGX1      },
> +       { X86_FEATURE_SGX_EUPDATESVN,           X86_FEATURE_SGX1      },
>         { X86_FEATURE_SGX_EDECCSSA,             X86_FEATURE_SGX1      },
>         { X86_FEATURE_XFD,                      X86_FEATURE_XSAVES    },
>         { X86_FEATURE_XFD,                      X86_FEATURE_XGETBV1   },

This one I missed, will add.
Re: [PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag
Posted by Ingo Molnar 7 months ago 
* Elena Reshetova <elena.reshetova@intel.com> wrote:

> Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction
> is supported. This will be used by SGX driver to perform CPU
> SVN updates.
> 
> Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h       | 1 +
>  arch/x86/kernel/cpu/scattered.c          | 1 +
>  tools/arch/x86/include/asm/cpufeatures.h | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 6c2c152d8a67..ed0c0fa5822a 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -481,6 +481,7 @@
>  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
>  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */
>  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM registers due to downclocking */
> +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for ENCLS[EUPDATESVN] instruction */

Please base the patches on the latest x86 tree, there's been two 
additions already in this area.

>  /*
>   * BUG word(s)
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index 16f3ca30626a..a7e1fcedca3c 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = {
>  	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0, 0x00000010, 3 },
>  	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0 },
>  	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0 },
> +	{ X86_FEATURE_SGX_EUPDATESVN,	CPUID_EAX, 10, 0x00000012, 0 },
>  	{ X86_FEATURE_SGX_EDECCSSA,		CPUID_EAX, 11, 0x00000012, 0 },
>  	{ X86_FEATURE_HW_PSTATE,		CPUID_EDX,  7, 0x80000007, 0 },
>  	{ X86_FEATURE_CPB,			CPUID_EDX,  9, 0x80000007, 0 },

So it should be obvious at a glance that this new line doesn't follow 
the coding convention of the surrounding lines...

Thanks,

	Ingo
RE: [PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag
Posted by Reshetova, Elena 7 months ago 
> * Elena Reshetova <elena.reshetova@intel.com> wrote:
> 
> > Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction
> > is supported. This will be used by SGX driver to perform CPU
> > SVN updates.
> >
> > Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
> > ---
> >  arch/x86/include/asm/cpufeatures.h       | 1 +
> >  arch/x86/kernel/cpu/scattered.c          | 1 +
> >  tools/arch/x86/include/asm/cpufeatures.h | 1 +
> >  3 files changed, 3 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> > index 6c2c152d8a67..ed0c0fa5822a 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -481,6 +481,7 @@
> >  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /*
> Heterogeneous Core Topology */
> >  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /*
> Workload Classification */
> >  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM
> registers due to downclocking */
> > +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for
> ENCLS[EUPDATESVN] instruction */
> 
> Please base the patches on the latest x86 tree, there's been two
> additions already in this area.

Will do in the next iteration.

> 
> >  /*
> >   * BUG word(s)
> > diff --git a/arch/x86/kernel/cpu/scattered.c
> b/arch/x86/kernel/cpu/scattered.c
> > index 16f3ca30626a..a7e1fcedca3c 100644
> > --- a/arch/x86/kernel/cpu/scattered.c
> > +++ b/arch/x86/kernel/cpu/scattered.c
> > @@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = {
> >  	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0,
> 0x00000010, 3 },
> >  	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0
> },
> >  	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0
> },
> > +	{ X86_FEATURE_SGX_EUPDATESVN,	CPUID_EAX, 10, 0x00000012,
> 0 },
> >  	{ X86_FEATURE_SGX_EDECCSSA,		CPUID_EAX, 11,
> 0x00000012, 0 },
> >  	{ X86_FEATURE_HW_PSTATE,		CPUID_EDX,  7, 0x80000007, 0
> },
> >  	{ X86_FEATURE_CPB,			CPUID_EDX,  9, 0x80000007, 0
> },
> 
> So it should be obvious at a glance that this new line doesn't follow
> the coding convention of the surrounding lines...

Will fix also.

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