On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
> check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> 3 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231..19a859e2a1f80c2321789af4ec7c5e299f0fb873 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -105,8 +105,7 @@
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> #define CTL_SC7280_MASK \
> - (BIT(DPU_CTL_VM_CFG) | \
> - BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> + (BIT(DPU_CTL_VM_CFG))
>
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 82f04de6300eca7d05ece3ac880c26f3a56505b9..1e5fc1d5873975189a1759212b8a6c6078de22f9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -133,13 +133,11 @@ enum {
> * CTL sub-blocks
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> - * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
> * @DPU_CTL_MAX
> */
> enum {
> DPU_CTL_SPLIT_DISPLAY = 0x1,
> DPU_CTL_VM_CFG,
> - DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
> DPU_CTL_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 772df53bfc4fcc2ff976f66ef7339be1ae3da8f4..edb82c81b0a449b1a7273fc258961b9447be8d9d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -804,7 +804,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
> c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
> c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
> - if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> + if (mdss_ver->core_major_ver >= 7)
> c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
> else
> c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>