Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
in the SpacemiT K1 SoC. The controller is based on the Synopsys
DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
DRD mode.

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..2fb9f1014c4e901417818a37b6289814a2d3d49a
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
+
+maintainers:
+  - Ze Huang <huangze@whut.edu.cn>
+
+description: |
+  The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
+  for USB 3.0 and DRD for USB 2.0.
+
+  Key features:
+  - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
+  - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
+  - Internal DMA controller and flexible endpoint FIFO sizing
+
+  Communication Interface:
+  - Use of PIPE3 (125MHz) interface for USB3.0 PHY
+  - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
+
+allOf:
+  - $ref: snps,dwc3-common.yaml#
+
+properties:
+  compatible:
+    const: spacemit,k1-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: usbdrd30
+
+  resets:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 1
+    description:
+      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
+      The 'interconnects' property explicitly describes this path, ensuring
+      correct address translation.
+
+  interconnect-names:
+    const: dma-mem
+
+  vbus-supply:
+    description: A phandle to the regulator supplying the VBUS voltage.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - interrupts
+  - interconnects
+  - interconnect-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    usb@c0a00000 {
+        compatible = "spacemit,k1-dwc3";
+        reg = <0xc0a00000 0x10000>;
+        clocks = <&syscon_apmu 16>;
+        clock-names = "usbdrd30";
+        resets = <&syscon_apmu 8>;
+        interrupt-parent = <&plic>;
+        interrupts = <125>;
+        interconnects = <&mbus0>;
+        interconnect-names = "dma-mem";
+    };

-- 
2.49.0

On Sun, May 18, 2025 at 03:19:19AM GMT, Ze Huang wrote:
> +properties:
> +  compatible:
> +    const: spacemit,k1-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: usbdrd30
> +

How many phys?

> +  resets:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interconnects:

compatible, reg and then order by name: clocks +names, interconnects +
names, interrupts, resets, vdd-supply.

> +    maxItems: 1
> +    description:
> +      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
> +      The 'interconnects' property explicitly describes this path, ensuring
> +      correct address translation.
> +
> +  interconnect-names:
> +    const: dma-mem
> +
> +  vbus-supply:
> +    description: A phandle to the regulator supplying the VBUS voltage.
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - interrupts
> +  - interconnects
> +  - interconnect-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    usb@c0a00000 {
> +        compatible = "spacemit,k1-dwc3";
> +        reg = <0xc0a00000 0x10000>;
> +        clocks = <&syscon_apmu 16>;
> +        clock-names = "usbdrd30";
> +        resets = <&syscon_apmu 8>;
> +        interrupt-parent = <&plic>;
> +        interrupts = <125>;
> +        interconnects = <&mbus0>;
> +        interconnect-names = "dma-mem";

Feels like missing port or ports. Are you sure your example is complete?

> +    };
> 
> -- 
> 2.49.0
>

On Mon, May 19, 2025 at 11:35:28AM +0200, Krzysztof Kozlowski wrote:
> On Sun, May 18, 2025 at 03:19:19AM GMT, Ze Huang wrote:
> > +properties:
> > +  compatible:
> > +    const: spacemit,k1-dwc3
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  clock-names:
> > +    const: usbdrd30
> > +
> 
> How many phys?
> 

Two phys: USB2.0 phy and USB3.0 phy

Will update the bindings in next version.

> > +  resets:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  interconnects:
> 
> compatible, reg and then order by name: clocks +names, interconnects +
> names, interrupts, resets, vdd-supply.
> 

Got it wrong again - thanks for your patience.

I'll update the property order as you suggested.

> > +    maxItems: 1
> > +    description:
> > +      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
> > +      The 'interconnects' property explicitly describes this path, ensuring
> > +      correct address translation.
> > +
> > +  interconnect-names:
> > +    const: dma-mem
> > +
> > +  vbus-supply:
> > +    description: A phandle to the regulator supplying the VBUS voltage.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - resets
> > +  - interrupts
> > +  - interconnects
> > +  - interconnect-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    usb@c0a00000 {
> > +        compatible = "spacemit,k1-dwc3";
> > +        reg = <0xc0a00000 0x10000>;
> > +        clocks = <&syscon_apmu 16>;
> > +        clock-names = "usbdrd30";
> > +        resets = <&syscon_apmu 8>;
> > +        interrupt-parent = <&plic>;
> > +        interrupts = <125>;
> > +        interconnects = <&mbus0>;
> > +        interconnect-names = "dma-mem";
> 
> Feels like missing port or ports. Are you sure your example is complete?
> 

Will include ports in next version

    hub@1 {
        compatible = "usb2109,2817";
        reg = <0x1>;
        vdd-supply = <&usb3_vhub>;
        peer-hub = <&hub_3_0>;
        reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
    };

    hub@2 {
        compatible = "usb2109,817";
        reg = <0x1>;
        vdd-supply = <&usb3_vhub>;
        peer-hub = <&hub_2_0>;
        reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
    };