From: Conor Dooley <conor.dooley@microchip.com>

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
For some reason, instead of adding dma-noncoherent to the binding
the pointless, NOP, property dma-coherent was. Swap dma-coherent for
dma-noncoherent.

Fixes: 04aa999eb96fd ("dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Bjorn Helgaas <bhelgaas@google.com>
CC: Lorenzo Pieralisi <lpieralisi@kernel.org>
CC: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Conor Dooley <conor+dt@kernel.org>
CC: linux-pci@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 103574d18dbc2..56397df2a6eec 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -50,7 +50,7 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
-  dma-coherent: true
+  dma-noncoherent: true
 
   ranges:
     minItems: 1
-- 
2.45.2

Hello,

> PolarFire SoC may be configured in a way that requires non-coherent DMA
> handling. On RISC-V, buses are coherent by default & the dma-noncoherent
> property is required to denote buses or devices that are non-coherent.
> For some reason, instead of adding dma-noncoherent to the binding
> the pointless, NOP, property dma-coherent was. Swap dma-coherent for
> dma-noncoherent.

I have favour to ask.  Can you capitalise (so-called "title case") the
subject when submitting patches that are PCI-specific DT bindings?

This is the preferred style for PCI, at least at the moment.

Also, it would save us the need to do it every time. :)

Thank you!

	Krzysztof

On Fri, May 16, 2025 at 10:06:59PM +0900, Krzysztof Wilczyński wrote:
> Hello,
> 
> > PolarFire SoC may be configured in a way that requires non-coherent DMA
> > handling. On RISC-V, buses are coherent by default & the dma-noncoherent
> > property is required to denote buses or devices that are non-coherent.
> > For some reason, instead of adding dma-noncoherent to the binding
> > the pointless, NOP, property dma-coherent was. Swap dma-coherent for
> > dma-noncoherent.
> 
> I have favour to ask.  Can you capitalise (so-called "title case") the
> subject when submitting patches that are PCI-specific DT bindings?

Sure, I can add that to my list of things I try to remember while
submitting for PCI.

> 
> This is the preferred style for PCI, at least at the moment.
> 
> Also, it would save us the need to do it every time. :)
> 
> Thank you!
> 
> 	Krzysztof