On 14/05/2025 11:25, Dario Binacchi wrote:
> From: Wolfgang Birkner <wolfgang.birkner@bshg.com>
>
> VDD_DRAM was disabled on standby, therefore the reference hardware did not
> wake up reliable. Use PMIC reset target state READY instead of SNVS, to
> keep VDD_DRAM active during standby.
There is something I'm not quite sure I understand. Lookin at the
BD71847 data-sheet, the VDD_DRAM is OFF at READY.
(Page 27, Table 3-8. Voltage Rails ON/OFF for Respective Power State)
https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator_system/bd71847amwv-e.pdf
Please, explain.
Yours,
-- Matti
>
> Signed-off-by: Wolfgang Birkner <wolfgang.birkner@bshg.com>
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
>
> ---
>
> arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
> index ea8d741c6904..633874b3bf66 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
> @@ -94,7 +94,6 @@ bd71847: pmic@4b {
> pinctrl-0 = <&pinctrl_pmic>;
> interrupt-parent = <&gpio1>;
> interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> - rohm,reset-snvs-powered;
>
> #clock-cells = <0>;
> clocks = <&osc_32k>;