Hello Neha
On 5/14/2025 12:50 PM, Neha Malcom Francis wrote:
> Add DT node for PBIST_14 that is responsible for triggering the PBIST
> self-tests for the MAIN_R5_2_x cores.
>
> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
> ---
> Changes since v2:
> - remove ti,bist-under-test property and use ti,sci-dev-id
>
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 0160fe0da983..fd098aac3989 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -113,6 +113,17 @@ serdes2: serdes@5020000 {
> status = "disabled";
> };
> };
> +
> + bist_main14: bist@33c0000 {
> + compatible = "ti,j784s4-bist";
> + reg = <0x00 0x033c0000 0x00 0x400>,
> + <0x00 0x0010c1a0 0x00 0x01c>;
> + reg-names = "cfg", "ctrl_mmr";
> + clocks = <&k3_clks 237 7>;
> + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>;
> + bootph-pre-ram;
> + ti,sci-dev-id = <234>;
> + };
Please extend this support to j742s2 SOC as well.
With above change
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
> };
>
> &scm_conf {