[v2] Update PCIe PHY settings for SA8775P

[PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by Mrinmay Sarkar 7 months, 1 week ago

From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>

The maximum link speed was previously restricted to Gen3 due to the
absence of Gen4 equalization support in the driver.

Add change to remove max link speed property, Since Gen4 equalization
support has already been added into the driver.

Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 5bd0c03476b143444543c68cd1c1d475c3302555..b001e9a30e863d8964219c8bd61bc328be71b256 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6462,7 +6462,6 @@ pcie0_ep: pcie-ep@1c00000 {
 		power-domains = <&gcc PCIE_0_GDSC>;
 		phys = <&pcie0_phy>;
 		phy-names = "pciephy";
-		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
 		num-lanes = <2>;
 		linux,pci-domain = <0>;
 
@@ -6620,7 +6619,6 @@ pcie1_ep: pcie-ep@1c10000 {
 		power-domains = <&gcc PCIE_1_GDSC>;
 		phys = <&pcie1_phy>;
 		phy-names = "pciephy";
-		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
 		num-lanes = <4>;
 		linux,pci-domain = <1>;
 

-- 
2.25.1

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by neil.armstrong@linaro.org 7 months, 1 week ago

On 14/05/2025 13:37, Mrinmay Sarkar wrote:
> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
> 
> The maximum link speed was previously restricted to Gen3 due to the
> absence of Gen4 equalization support in the driver.
> 
> Add change to remove max link speed property, Since Gen4 equalization
> support has already been added into the driver.

Which driver, PHY or Controller ? does this change depends on the patch 1 PHY settings update ?

> 
> Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
> ---
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 --
>   1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 5bd0c03476b143444543c68cd1c1d475c3302555..b001e9a30e863d8964219c8bd61bc328be71b256 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -6462,7 +6462,6 @@ pcie0_ep: pcie-ep@1c00000 {
>   		power-domains = <&gcc PCIE_0_GDSC>;
>   		phys = <&pcie0_phy>;
>   		phy-names = "pciephy";
> -		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
>   		num-lanes = <2>;
>   		linux,pci-domain = <0>;
>   
> @@ -6620,7 +6619,6 @@ pcie1_ep: pcie-ep@1c10000 {
>   		power-domains = <&gcc PCIE_1_GDSC>;
>   		phys = <&pcie1_phy>;
>   		phy-names = "pciephy";
> -		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
>   		num-lanes = <4>;
>   		linux,pci-domain = <1>;
>   
>

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by Konrad Dybcio 7 months, 1 week ago

On 5/14/25 6:38 PM, neil.armstrong@linaro.org wrote:
> On 14/05/2025 13:37, Mrinmay Sarkar wrote:
>> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
>>
>> The maximum link speed was previously restricted to Gen3 due to the
>> absence of Gen4 equalization support in the driver.
>>
>> Add change to remove max link speed property, Since Gen4 equalization
>> support has already been added into the driver.
> 
> Which driver, PHY or Controller ?

Controller, see 

09483959e34d ("PCI: dwc: Add support for configuring lane equalization presets")

and commits around it

does this change depends on the patch 1 PHY settings update ?

That I'm curious about too, but I would guesstimate no

Konrad

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by Mrinmay Sarkar 7 months, 1 week ago

On Fri, May 16, 2025 at 2:30 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 5/14/25 6:38 PM, neil.armstrong@linaro.org wrote:
> > On 14/05/2025 13:37, Mrinmay Sarkar wrote:
> >> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
> >>
> >> The maximum link speed was previously restricted to Gen3 due to the
> >> absence of Gen4 equalization support in the driver.
> >>
> >> Add change to remove max link speed property, Since Gen4 equalization
> >> support has already been added into the driver.
> >
> > Which driver, PHY or Controller ?
>
> Controller, see
>
> 09483959e34d ("PCI: dwc: Add support for configuring lane equalization presets")

Yes, this patch is helping to solve gen4 stability issue.
>
> and commits around it
>
> does this change depends on the patch 1 PHY settings update ?
>
> That I'm curious about too, but I would guesstimate no
>
this change doesn't depends on the patch 1 PHY settings update

> Konrad

Mrinmay

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by Dmitry Baryshkov 7 months ago

On Fri, May 16, 2025 at 03:59:02PM +0530, Mrinmay Sarkar wrote:
> On Fri, May 16, 2025 at 2:30 PM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
> >
> > On 5/14/25 6:38 PM, neil.armstrong@linaro.org wrote:
> > > On 14/05/2025 13:37, Mrinmay Sarkar wrote:
> > >> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
> > >>
> > >> The maximum link speed was previously restricted to Gen3 due to the
> > >> absence of Gen4 equalization support in the driver.
> > >>
> > >> Add change to remove max link speed property, Since Gen4 equalization
> > >> support has already been added into the driver.
> > >
> > > Which driver, PHY or Controller ?
> >
> > Controller, see
> >
> > 09483959e34d ("PCI: dwc: Add support for configuring lane equalization presets")
> 
> Yes, this patch is helping to solve gen4 stability issue.
> >
> > and commits around it
> >
> > does this change depends on the patch 1 PHY settings update ?
> >
> > That I'm curious about too, but I would guesstimate no
> >
> this change doesn't depends on the patch 1 PHY settings update

Then what has changed, as previously it was documented to have stability
issues.

-- 
With best wishes
Dmitry

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by Mrinmay Sarkar 7 months ago

On Sat, May 17, 2025 at 3:33 AM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> On Fri, May 16, 2025 at 03:59:02PM +0530, Mrinmay Sarkar wrote:
> > On Fri, May 16, 2025 at 2:30 PM Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> > >
> > > On 5/14/25 6:38 PM, neil.armstrong@linaro.org wrote:
> > > > On 14/05/2025 13:37, Mrinmay Sarkar wrote:
> > > >> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
> > > >>
> > > >> The maximum link speed was previously restricted to Gen3 due to the
> > > >> absence of Gen4 equalization support in the driver.
> > > >>
> > > >> Add change to remove max link speed property, Since Gen4 equalization
> > > >> support has already been added into the driver.
> > > >
> > > > Which driver, PHY or Controller ?
> > >
> > > Controller, see
> > >
> > > 09483959e34d ("PCI: dwc: Add support for configuring lane equalization presets")
> >
> > Yes, this patch is helping to solve gen4 stability issue.
> > >
> > > and commits around it
> > >
> > > does this change depends on the patch 1 PHY settings update ?
> > >
> > > That I'm curious about too, but I would guesstimate no
> > >
> > this change doesn't depends on the patch 1 PHY settings update
>
> Then what has changed, as previously it was documented to have stability
> issues.
>
Actually this controller change is solving the stability issue with
gen4: "PCI: qcom: Add equalization settings for 16.0 GT/s"
https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org/

Thanks,
Mrinmay
> --
> With best wishes
> Dmitry

Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

Posted by Neil Armstrong 7 months ago

On 19/05/2025 14:16, Mrinmay Sarkar wrote:
> On Sat, May 17, 2025 at 3:33 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>
>> On Fri, May 16, 2025 at 03:59:02PM +0530, Mrinmay Sarkar wrote:
>>> On Fri, May 16, 2025 at 2:30 PM Konrad Dybcio
>>> <konrad.dybcio@oss.qualcomm.com> wrote:
>>>>
>>>> On 5/14/25 6:38 PM, neil.armstrong@linaro.org wrote:
>>>>> On 14/05/2025 13:37, Mrinmay Sarkar wrote:
>>>>>> From: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
>>>>>>
>>>>>> The maximum link speed was previously restricted to Gen3 due to the
>>>>>> absence of Gen4 equalization support in the driver.
>>>>>>
>>>>>> Add change to remove max link speed property, Since Gen4 equalization
>>>>>> support has already been added into the driver.
>>>>>
>>>>> Which driver, PHY or Controller ?
>>>>
>>>> Controller, see
>>>>
>>>> 09483959e34d ("PCI: dwc: Add support for configuring lane equalization presets")
>>>
>>> Yes, this patch is helping to solve gen4 stability issue.
>>>>
>>>> and commits around it
>>>>
>>>> does this change depends on the patch 1 PHY settings update ?
>>>>
>>>> That I'm curious about too, but I would guesstimate no
>>>>
>>> this change doesn't depends on the patch 1 PHY settings update
>>
>> Then what has changed, as previously it was documented to have stability
>> issues.
>>
> Actually this controller change is solving the stability issue with
> gen4: "PCI: qcom: Add equalization settings for 16.0 GT/s"
> https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org/

Ok so those patches should be send separately and will reduce maintainers work
by trying to figure out if there's a dependency.

Neil

> 
> Thanks,
> Mrinmay
>> --
>> With best wishes
>> Dmitry