The FORCE_LINK_GOOD bit in the PHY_CONTROL register forces the reported
link status to 1 if the selected speed is 1Gbps.
According to the DP83869 PHY datasheet, this bit should default to 0 after
a hardware reset. However, the opposite has been observed on some DP83869
components.
As a consequence, a valid link will be reported in 1000Base-X operational
modes, even if the autonegotiation process failed.
Make sure that the FORCE_LINK_GOOD bit is cleared during initial
configuration.
Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
---
drivers/net/phy/dp83869.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 010434c94e01f44ac3c0b7e147468f4f7dca33f4..000660aae16ed46166774e7235cd8a6df94be047 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -89,6 +89,7 @@
#define DP83869_STRAP_MIRROR_ENABLED BIT(12)
/* PHYCTRL bits */
+#define DP83869_FORCE_LINK_GOOD BIT(10)
#define DP83869_RX_FIFO_SHIFT 12
#define DP83869_TX_FIFO_SHIFT 14
@@ -810,6 +811,15 @@ static int dp83869_config_init(struct phy_device *phydev)
struct dp83869_private *dp83869 = phydev->priv;
int ret, val;
+ /* The FORCE_LINK_GOOD bit in the PHYCTRL register should be
+ * unset after a hardware reset but it is not. make sure it is
+ * cleared so that the PHY can function properly.
+ */
+ ret = phy_clear_bits(phydev, MII_DP83869_PHYCTRL,
+ DP83869_FORCE_LINK_GOOD);
+ if (ret)
+ return ret;
+
/* Force speed optimization for the PHY even if it strapped */
ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
DP83869_DOWNSHIFT_EN);
--
2.49.0