On Sun, May 11, 2025 at 09:27:46PM -0400, Damien Riégel wrote:
> Document device tree bindings for Silicon Labs CPC over a SPI bus. This
> device requires both a chip select and an interrupt line to be able to
> work.
What's CPC? Never defined here.
Bindings are for devices, not a SPI protocol. What if the device needs
reset or power or ??? before you can talk to it. Maybe it's a situation
where that will never matter, but you've got to spell it out here.
>
> Signed-off-by: Damien Riégel <damien.riegel@silabs.com>
> ---
> .../bindings/net/silabs,cpc-spi.yaml | 54 +++++++++++++++++++
> 1 file changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/silabs,cpc-spi.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/silabs,cpc-spi.yaml b/Documentation/devicetree/bindings/net/silabs,cpc-spi.yaml
> new file mode 100644
> index 00000000000..82d3cd47daa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/silabs,cpc-spi.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2024 Silicon Labs Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/silabs,cpc-spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SPI driver for CPC
> +
> +maintainers:
> + - Damien Riégel <damien.riegel@silabs.com>
> +
> +description: |
Don't need '|'
> + This binding is for the implementation of CPC protocol over SPI. The protocol
> + consists of a chain of header+payload frames. The interrupt is used by the
> + device to signal it has a frame to transmit, but also between headers and
> + payloads to signal that it is ready to receive payload.
> +
> +properties:
> + compatible:
> + enum:
> + - silabs,cpc-spi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupt
> +
> +allOf:
> + - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpcspi@0 {
> + compatible = "silabs,cpc-spi";
> + reg = <0>;
> + spi-max-frequency = <1000000>;
> + interrupt-parent = <&gpio>;
> + interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
> + };
> + };
> --
> 2.49.0
>