From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Convert cdn-dp-rockchip.txt to yaml.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
---
Changes in v2:
- Rename binding file name to match compatible
- Add more description about grf/phy/extcon
- Fix coding style
.../display/rockchip/cdn-dp-rockchip.txt | 74 --------
.../rockchip/rockchip,rk3399-cdn-dp.yaml | 158 ++++++++++++++++++
2 files changed, 158 insertions(+), 74 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml
diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
deleted file mode 100644
index 8df7d2e393d6..000000000000
--- a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Rockchip RK3399 specific extensions to the cdn Display Port
-================================
-
-Required properties:
-- compatible: must be "rockchip,rk3399-cdn-dp"
-
-- reg: physical base address of the controller and length
-
-- clocks: from common clock binding: handle to dp clock.
-
-- clock-names: from common clock binding:
- Required elements: "core-clk" "pclk" "spdif" "grf"
-
-- resets : a list of phandle + reset specifier pairs
-- reset-names : string of reset names
- Required elements: "apb", "core", "dptx", "spdif"
-- power-domains : power-domain property defined with a phandle
- to respective power domain.
-- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
-- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
-
-- rockchip,grf: this soc should set GRF regs, so need get grf here.
-
-- ports: contain a port nodes with endpoint definitions as defined in
- Documentation/devicetree/bindings/media/video-interfaces.txt.
- contained 2 endpoints, connecting to the output of vop.
-
-- phys: from general PHY binding: the phandle for the PHY device.
-
-- extcon: extcon specifier for the Power Delivery
-
-- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
-
--------------------------------------------------------------------------------
-
-Example:
- cdn_dp: dp@fec00000 {
- compatible = "rockchip,rk3399-cdn-dp";
- reg = <0x0 0xfec00000 0x0 0x100000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
- <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
- clock-names = "core-clk", "pclk", "spdif", "grf";
- assigned-clocks = <&cru SCLK_DP_CORE>;
- assigned-clock-rates = <100000000>;
- power-domains = <&power RK3399_PD_HDCP>;
- phys = <&tcphy0_dp>, <&tcphy1_dp>;
- resets = <&cru SRST_DPTX_SPDIF_REC>;
- reset-names = "spdif";
- extcon = <&fusb0>, <&fusb1>;
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dp_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- dp_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_dp>;
- };
-
- dp_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_dp>;
- };
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml
new file mode 100644
index 000000000000..99d1f0ad9cda
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,cdn-dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3399 specific extensions to the CDN Display Port
+
+maintainers:
+ - Andy Yan <andy.yan@rock-chip.com>
+ - Heiko Stuebner <heiko@sntech.de>
+ - Sandy Huang <hjc@rock-chips.com>
+
+allOf:
+ - $ref: /schemas/sound/dai-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: rockchip,rk3399-cdn-dp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: DP core work clock
+ - description: APB clock
+ - description: SPDIF interface clock
+ - description: GRF clock
+
+ clock-names:
+ items:
+ - const: core-clk
+ - const: pclk
+ - const: spdif
+ - const: grf
+
+ extcon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle to the extcon device providing the cable state for the DP PHY.
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle to the PHY device for DP output.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input of the CDN DP
+ properties:
+ endpoint@0:
+ description: Connection to the VOPB
+ endpoint@1:
+ description: Connection to the VOPL
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output of the CDN DP
+
+ required:
+ - port@0
+ - port@1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: spdif
+ - const: dptx
+ - const: apb
+ - const: core
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to GRF register to control HPD.
+
+ "#sound-dai-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - phys
+ - ports
+ - resets
+ - reset-names
+ - rockchip,grf
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3399-power.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+ <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+ reset-names = "spdif", "dptx", "apb", "core";
+ rockchip,grf = <&grf>;
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+
+ dp_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
--
2.49.0On Fri, 09 May 2025 15:02:47 +0800, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > Convert cdn-dp-rockchip.txt to yaml. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > > Changes in v2: > - Rename binding file name to match compatible > - Add more description about grf/phy/extcon > - Fix coding style > > > .../display/rockchip/cdn-dp-rockchip.txt | 74 -------- > .../rockchip/rockchip,rk3399-cdn-dp.yaml | 158 ++++++++++++++++++ > 2 files changed, 158 insertions(+), 74 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml: $id: Cannot determine base path from $id, relative path/filename doesn't match actual path or filename $id: http://devicetree.org/schemas/display/rockchip/rockchip,cdn-dp.yaml file: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250509070247.868-3-kernel@airkyi.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 09/05/2025 09:02, Chaoyi Chen wrote: > + > + clock-names: > + items: > + - const: core-clk > + - const: pclk > + - const: spdif > + - const: grf > + > + extcon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Phandle to the extcon device providing the cable state for the DP PHY. > + > + interrupts: > + maxItems: 1 > + > + phys: > + $ref: /schemas/types.yaml#/definitions/phandle-array Just phandle. If this is an array (but why?), you need maxItems for outer and inner dimensions. > + description: > + Phandle to the PHY device for DP output. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input of the CDN DP > + properties: > + endpoint@0: > + description: Connection to the VOPB > + endpoint@1: > + description: Connection to the VOPL > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output of the CDN DP > + > + required: > + - port@0 > + - port@1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 4 > + > + reset-names: > + items: > + - const: spdif > + - const: dptx > + - const: apb > + - const: core > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF register to control HPD. > + > + "#sound-dai-cells": > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - phys > + - ports > + - resets > + - reset-names > + - rockchip,grf > + > +additionalProperties: false Well, if you added dai-common $ref then this could have stayed as unevaluatedProperties, so you will allow names for the DAI as well. > Best regards, Krzysztof
Hi Krzysztof, On 2025/5/9 15:11, Krzysztof Kozlowski wrote: > On 09/05/2025 09:02, Chaoyi Chen wrote: >> + >> + clock-names: >> + items: >> + - const: core-clk >> + - const: pclk >> + - const: spdif >> + - const: grf >> + >> + extcon: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + description: >> + Phandle to the extcon device providing the cable state for the DP PHY. >> + >> + interrupts: >> + maxItems: 1 >> + >> + phys: >> + $ref: /schemas/types.yaml#/definitions/phandle-array > Just phandle. If this is an array (but why?), you need maxItems for > outer and inner dimensions. I think it could be phandle or phandle-array. Since the RK3399 DP has two PHYs, if we put in two PHYs here, the driver will pick one PHY port that is already plugged into the DP for output. If we fill in only one PHY here, then output is only allowed on the corresponding PHY. Will add restrictions and add more descriptions in v3. > >> + description: >> + Phandle to the PHY device for DP output. >> + >> + ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + port@0: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: Input of the CDN DP >> + properties: >> + endpoint@0: >> + description: Connection to the VOPB >> + endpoint@1: >> + description: Connection to the VOPL >> + port@1: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: Output of the CDN DP >> + >> + required: >> + - port@0 >> + - port@1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 4 >> + >> + reset-names: >> + items: >> + - const: spdif >> + - const: dptx >> + - const: apb >> + - const: core >> + >> + rockchip,grf: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + Phandle to GRF register to control HPD. >> + >> + "#sound-dai-cells": >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - interrupts >> + - phys >> + - ports >> + - resets >> + - reset-names >> + - rockchip,grf >> + >> +additionalProperties: false > Well, if you added dai-common $ref then this could have stayed as > unevaluatedProperties, so you will allow names for the DAI as well. Thanks for your clarification. Will fix in v3. > > > Best regards, > Krzysztof > >
On 09/05/2025 09:34, Chaoyi Chen wrote: > Hi Krzysztof, > > On 2025/5/9 15:11, Krzysztof Kozlowski wrote: >> On 09/05/2025 09:02, Chaoyi Chen wrote: >>> + >>> + clock-names: >>> + items: >>> + - const: core-clk >>> + - const: pclk >>> + - const: spdif >>> + - const: grf >>> + >>> + extcon: >>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>> + description: >>> + Phandle to the extcon device providing the cable state for the DP PHY. >>> + >>> + interrupts: >>> + maxItems: 1 >>> + >>> + phys: >>> + $ref: /schemas/types.yaml#/definitions/phandle-array >> Just phandle. If this is an array (but why?), you need maxItems for >> outer and inner dimensions. Uh, sorry, that was supposed to be under extcon. > > I think it could be phandle or phandle-array. Since the RK3399 DP has Here it is obviously not needed, that's a dtschema type. > two PHYs, if we put in two PHYs here, the driver will pick one PHY port > that is already plugged into the DP for output. If we fill in only one > PHY here, then output is only allowed on the corresponding PHY. > > Will add restrictions and add more descriptions in v3. > > >> >>> + description: >>> + Phandle to the PHY device for DP output. You need to list the items with description iinstead. Best regards, Krzysztof
Hi Krzysztof, On 2025/5/9 17:21, Krzysztof Kozlowski wrote: > On 09/05/2025 09:34, Chaoyi Chen wrote: >> Hi Krzysztof, >> >> On 2025/5/9 15:11, Krzysztof Kozlowski wrote: >>> On 09/05/2025 09:02, Chaoyi Chen wrote: >>>> + >>>> + clock-names: >>>> + items: >>>> + - const: core-clk >>>> + - const: pclk >>>> + - const: spdif >>>> + - const: grf >>>> + >>>> + extcon: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + description: >>>> + Phandle to the extcon device providing the cable state for the DP PHY. >>>> + >>>> + interrupts: >>>> + maxItems: 1 >>>> + >>>> + phys: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>> Just phandle. If this is an array (but why?), you need maxItems for >>> outer and inner dimensions. > Uh, sorry, that was supposed to be under extcon. Oh, this also applies to extcon. Each extcon is used to indicate the status of the PHY. > >> I think it could be phandle or phandle-array. Since the RK3399 DP has > Here it is obviously not needed, that's a dtschema type. Do you mean that there is no need to explicitly specify something like "$ref: /schemas/types.yaml#/definitions/phandle" ? > >> two PHYs, if we put in two PHYs here, the driver will pick one PHY port >> that is already plugged into the DP for output. If we fill in only one >> PHY here, then output is only allowed on the corresponding PHY. >> >> Will add restrictions and add more descriptions in v3. >> >> >>>> + description: >>>> + Phandle to the PHY device for DP output. > You need to list the items with description iinstead. Okay, will fix in v3. > > > > Best regards, > Krzysztof > >
Am Freitag, 9. Mai 2025, 09:34:47 Mitteleuropäische Sommerzeit schrieb Chaoyi Chen: > Hi Krzysztof, > > On 2025/5/9 15:11, Krzysztof Kozlowski wrote: > > On 09/05/2025 09:02, Chaoyi Chen wrote: > >> + > >> + clock-names: > >> + items: > >> + - const: core-clk > >> + - const: pclk > >> + - const: spdif > >> + - const: grf > >> + > >> + extcon: > >> + $ref: /schemas/types.yaml#/definitions/phandle-array > >> + description: > >> + Phandle to the extcon device providing the cable state for the DP PHY. > >> + > >> + interrupts: > >> + maxItems: 1 > >> + > >> + phys: > >> + $ref: /schemas/types.yaml#/definitions/phandle-array > > Just phandle. If this is an array (but why?), you need maxItems for > > outer and inner dimensions. > > I think it could be phandle or phandle-array. Since the RK3399 DP has > two PHYs, if we put in two PHYs here, the driver will pick one PHY port > that is already plugged into the DP for output. If we fill in only one > PHY here, then output is only allowed on the corresponding PHY. > > Will add restrictions and add more descriptions in v3. Just looked that up in the documentation. Only the rk3399 has used this controller at all so far. There is one cdn-dp controller on it, but two phys for the two type-c blocks on the soc. The controller can then select which one to drive. So yep, there are two phys. Heiko
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