From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Add dedicated schema for the PCIe controllers found on QCS615.
Due to qcs615's clock-names do not match any of the existing
dt-bindings, a new compatible for qcs615 is needed.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
.../bindings/pci/qcom,qcs615-pcie.yaml | 165 ++++++++++++++++++
1 file changed, 165 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,qcs615-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/qcom,qcs615-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,qcs615-pcie.yaml
new file mode 100644
index 000000000000..6f8741fc818a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,qcs615-pcie.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,qcs615-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS615 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ Qualcomm QCS615 SoC (and compatible) PCIe root complex controller is based on
+ the Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,qcs615-pcie
+
+ reg:
+ minItems: 6
+ maxItems: 6
+
+ reg-names:
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 5
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+
+ interrupts:
+ minItems: 9
+ maxItems: 9
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c08000 {
+ compatible = "qcom,qcs615-pcie";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>,
+ <0 0x01c0b000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ref";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7", "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interconnects = <&agree1_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x400 0x1>,
+ <0x100 &apps_smmu 0x401 0x1>;
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
+ 0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
+
+ pinctrl-0 = <&pcie_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ };
+ };
--
2.34.1On Wed, May 07, 2025 at 11:15:56AM GMT, Ziyue Zhang wrote: > From: Krishna chaitanya chundru <quic_krichai@quicinc.com> > > Add dedicated schema for the PCIe controllers found on QCS615. > Due to qcs615's clock-names do not match any of the existing > dt-bindings, a new compatible for qcs615 is needed. Other bindings for QCS615 were not finished, so I have doubts this is done as well. Send your bindings once you finish them. ... > +properties: > + compatible: > + const: qcom,qcs615-pcie > + > + reg: > + minItems: 6 > + maxItems: 6 > + > + reg-names: > + items: > + - const: parf # Qualcomm specific registers > + - const: dbi # DesignWare PCIe registers > + - const: elbi # External local bus interface registers > + - const: atu # ATU address space > + - const: config # PCIe configuration space > + - const: mhi # MHI registers > + > + clocks: > + minItems: 5 Drop or use correct value - 6. I don't understand why this changed and nothing in changelog explains this. Best regards, Krzysztof
On 5/7/2025 1:17 PM, Krzysztof Kozlowski wrote: > On Wed, May 07, 2025 at 11:15:56AM GMT, Ziyue Zhang wrote: >> From: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> >> Add dedicated schema for the PCIe controllers found on QCS615. >> Due to qcs615's clock-names do not match any of the existing >> dt-bindings, a new compatible for qcs615 is needed. > Other bindings for QCS615 were not finished, so I have doubts this is > done as well. Send your bindings once you finish them. > > ... > >> +properties: >> + compatible: >> + const: qcom,qcs615-pcie >> + >> + reg: >> + minItems: 6 >> + maxItems: 6 >> + >> + reg-names: >> + items: >> + - const: parf # Qualcomm specific registers >> + - const: dbi # DesignWare PCIe registers >> + - const: elbi # External local bus interface registers >> + - const: atu # ATU address space >> + - const: config # PCIe configuration space >> + - const: mhi # MHI registers >> + >> + clocks: >> + minItems: 5 > Drop or use correct value - 6. I don't understand why this changed and > nothing in changelog explains this. > > Best regards, > Krzysztof Hi Krzysztof As discussed in qcs8300, gcc_aux_clk is recommended to be removed from PCIe PHY device tree node, so I need to update the bindings. BRs Ziyue
On 12/05/2025 10:16, Ziyue Zhang wrote: > > On 5/7/2025 1:17 PM, Krzysztof Kozlowski wrote: >> On Wed, May 07, 2025 at 11:15:56AM GMT, Ziyue Zhang wrote: >>> From: Krishna chaitanya chundru <quic_krichai@quicinc.com> >>> >>> Add dedicated schema for the PCIe controllers found on QCS615. >>> Due to qcs615's clock-names do not match any of the existing >>> dt-bindings, a new compatible for qcs615 is needed. >> Other bindings for QCS615 were not finished, so I have doubts this is >> done as well. Send your bindings once you finish them. >> >> ... >> >>> +properties: >>> + compatible: >>> + const: qcom,qcs615-pcie >>> + >>> + reg: >>> + minItems: 6 >>> + maxItems: 6 >>> + >>> + reg-names: >>> + items: >>> + - const: parf # Qualcomm specific registers >>> + - const: dbi # DesignWare PCIe registers >>> + - const: elbi # External local bus interface registers >>> + - const: atu # ATU address space >>> + - const: config # PCIe configuration space >>> + - const: mhi # MHI registers >>> + >>> + clocks: >>> + minItems: 5 >> Drop or use correct value - 6. I don't understand why this changed and >> nothing in changelog explains this. >> >> Best regards, >> Krzysztof > > Hi Krzysztof > > As discussed in qcs8300, gcc_aux_clk is recommended to be removed from PCIe PHY > device tree node, so I need to update the bindings. I don't see how this is relevant to the code you posted and to my comment, so comment stays valid. Best regards, Krzysztof
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