The Aardvark PCIe controller enforces a fixed 512B payload size via
PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe
core negotiations.
Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and
PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core
during device initialization, leveraging root port configurations and
device-specific capabilities.
Aligning Aardvark with the unified MPS framework ensures consistency,
avoids artificial constraints, and allows the hardware to operate at
its maximum supported payload size while adhering to PCIe specifications.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/pci-aardvark.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index a29796cce420..d8852892994a 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
- reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
reg &= ~PCI_EXP_DEVCTL_READRQ;
- reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
reg |= PCI_EXP_DEVCTL_READRQ_512B;
advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
--
2.25.1On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: > The Aardvark PCIe controller enforces a fixed 512B payload size via > PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe > core negotiations. > > Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and > PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core > during device initialization, leveraging root port configurations and > device-specific capabilities. > > Aligning Aardvark with the unified MPS framework ensures consistency, > avoids artificial constraints, and allows the hardware to operate at > its maximum supported payload size while adhering to PCIe specifications. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/pci-aardvark.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index a29796cce420..d8852892994a 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; > reg &= ~PCI_EXP_DEVCTL_READRQ; > - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; > reg |= PCI_EXP_DEVCTL_READRQ_512B; > advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > -- > 2.25.1 > Please do not remove this code. It is required part of the initialization of the aardvark PCI controller at the specific phase, as defined in the Armada 3700 Functional Specification. There were reported more issues with those Armada PCIe controllers for which were already sent patches to mailing list in last 5 years. But unfortunately not all fixes were taken / applied yet.
On 2025/5/7 01:41, Pali Rohár wrote: > On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: >> The Aardvark PCIe controller enforces a fixed 512B payload size via >> PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe >> core negotiations. >> >> Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and >> PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core >> during device initialization, leveraging root port configurations and >> device-specific capabilities. >> >> Aligning Aardvark with the unified MPS framework ensures consistency, >> avoids artificial constraints, and allows the hardware to operate at >> its maximum supported payload size while adhering to PCIe specifications. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >> drivers/pci/controller/pci-aardvark.c | 2 -- >> 1 file changed, 2 deletions(-) >> >> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c >> index a29796cce420..d8852892994a 100644 >> --- a/drivers/pci/controller/pci-aardvark.c >> +++ b/drivers/pci/controller/pci-aardvark.c >> @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) >> reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >> reg &= ~PCI_EXP_DEVCTL_RELAX_EN; >> reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; >> - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; >> reg &= ~PCI_EXP_DEVCTL_READRQ; >> - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; >> reg |= PCI_EXP_DEVCTL_READRQ_512B; >> advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >> >> -- >> 2.25.1 >> > > Please do not remove this code. It is required part of the > initialization of the aardvark PCI controller at the specific phase, > as defined in the Armada 3700 Functional Specification. > > There were reported more issues with those Armada PCIe controllers for > which were already sent patches to mailing list in last 5 years. But > unfortunately not all fixes were taken / applied yet. Hi Pali, I replied to you in version v2. Is the maximum MPS supported by Armada 3700 512 bytes? What are the default values of DevCap.MPS and DevCtl.MPS? Because the default value of DevCtl.MPS is not 512 bytes, it needs to be configured here, right? If it's my guess, RK3588 also has the same requirements as you, just like the first patch I submitted. Please take a look at the communication history: https://patchwork.kernel.org/project/linux-pci/patch/20250416151926.140202-1-18255117159@163.com/ Please test it using patch 1/3 of this series. If there are any problems, please let me know. Best regards, Hans
On 2025/5/7 23:03, Hans Zhang wrote: > > > On 2025/5/7 01:41, Pali Rohár wrote: >> On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: >>> The Aardvark PCIe controller enforces a fixed 512B payload size via >>> PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe >>> core negotiations. >>> >>> Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and >>> PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core >>> during device initialization, leveraging root port configurations and >>> device-specific capabilities. >>> >>> Aligning Aardvark with the unified MPS framework ensures consistency, >>> avoids artificial constraints, and allows the hardware to operate at >>> its maximum supported payload size while adhering to PCIe >>> specifications. >>> >>> Signed-off-by: Hans Zhang <18255117159@163.com> >>> --- >>> drivers/pci/controller/pci-aardvark.c | 2 -- >>> 1 file changed, 2 deletions(-) >>> >>> diff --git a/drivers/pci/controller/pci-aardvark.c >>> b/drivers/pci/controller/pci-aardvark.c >>> index a29796cce420..d8852892994a 100644 >>> --- a/drivers/pci/controller/pci-aardvark.c >>> +++ b/drivers/pci/controller/pci-aardvark.c >>> @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie >>> *pcie) >>> reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >>> reg &= ~PCI_EXP_DEVCTL_RELAX_EN; >>> reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; >>> - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; >>> reg &= ~PCI_EXP_DEVCTL_READRQ; >>> - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; >>> reg |= PCI_EXP_DEVCTL_READRQ_512B; >>> advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >>> -- >>> 2.25.1 >>> >> >> Please do not remove this code. It is required part of the >> initialization of the aardvark PCI controller at the specific phase, >> as defined in the Armada 3700 Functional Specification. >> >> There were reported more issues with those Armada PCIe controllers for >> which were already sent patches to mailing list in last 5 years. But >> unfortunately not all fixes were taken / applied yet. > > Hi Pali, > > I replied to you in version v2. > > Is the maximum MPS supported by Armada 3700 512 bytes? What are the > default values of DevCap.MPS and DevCtl.MPS? > > Because the default value of DevCtl.MPS is not 512 bytes, it needs to be > configured here, right? > > If it's my guess, RK3588 also has the same requirements as you, just > like the first patch I submitted. > > Please take a look at the communication history: > https://patchwork.kernel.org/project/linux-pci/patch/20250416151926.140202-1-18255117159@163.com/ And this: https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-2-18255117159@163.com/ > > Please test it using patch 1/3 of this series. If there are any > problems, please let me know. > > > Best regards, > Hans
On Wednesday 07 May 2025 23:06:51 Hans Zhang wrote: > On 2025/5/7 23:03, Hans Zhang wrote: > > On 2025/5/7 01:41, Pali Rohár wrote: > > > On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: > > > > The Aardvark PCIe controller enforces a fixed 512B payload size via > > > > PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe > > > > core negotiations. > > > > > > > > Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and > > > > PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core > > > > during device initialization, leveraging root port configurations and > > > > device-specific capabilities. > > > > > > > > Aligning Aardvark with the unified MPS framework ensures consistency, > > > > avoids artificial constraints, and allows the hardware to operate at > > > > its maximum supported payload size while adhering to PCIe > > > > specifications. > > > > > > > > Signed-off-by: Hans Zhang <18255117159@163.com> > > > > --- > > > > drivers/pci/controller/pci-aardvark.c | 2 -- > > > > 1 file changed, 2 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/pci-aardvark.c > > > > b/drivers/pci/controller/pci-aardvark.c > > > > index a29796cce420..d8852892994a 100644 > > > > --- a/drivers/pci/controller/pci-aardvark.c > > > > +++ b/drivers/pci/controller/pci-aardvark.c > > > > @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct > > > > advk_pcie *pcie) > > > > reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > > > > reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > > > > - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; > > > > reg &= ~PCI_EXP_DEVCTL_READRQ; > > > > - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; > > > > reg |= PCI_EXP_DEVCTL_READRQ_512B; > > > > advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > -- > > > > 2.25.1 > > > > > > > > > > Please do not remove this code. It is required part of the > > > initialization of the aardvark PCI controller at the specific phase, > > > as defined in the Armada 3700 Functional Specification. > > > > > > There were reported more issues with those Armada PCIe controllers for > > > which were already sent patches to mailing list in last 5 years. But > > > unfortunately not all fixes were taken / applied yet. > > > > Hi Pali, > > > > I replied to you in version v2. > > > > Is the maximum MPS supported by Armada 3700 512 bytes? IIRC yes, 512-byte mode is supported. And I think in past I was testing some PCIe endpoint card which required 512-byte long payload and did not worked in 256-byte long mode (not sure if the card was not able to split transaction or something other was broken, it is quite longer time). > > What are the default values of DevCap.MPS and DevCtl.MPS? Do you mean values in the PCI-to-PCI bridge device of PCIe Root Port type? Aardvark controller does not have the real HW PCI-to-PCI bridge device. There is only in-kernel emulation drivers/pci/pci-bridge-emul.c which create fake kernel PCI device in the hierarchy to make kernel and userspace happy. Yes, this is deviation from the PCIe standard but well, buggy HW is also HW. And same applies for the pci-mvebu.c driver for older Marvell PCIe HW. > > Because the default value of DevCtl.MPS is not 512 bytes, it needs to be > > configured here, right? > > > > If it's my guess, RK3588 also has the same requirements as you, just > > like the first patch I submitted. > > > > Please take a look at the communication history: > > https://patchwork.kernel.org/project/linux-pci/patch/20250416151926.140202-1-18255117159@163.com/ > And this: > https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-2-18255117159@163.com/ These changes are referring the to root ports PCI devices, which are not applicable for aardvark PCIe controller. > > > > Please test it using patch 1/3 of this series. If there are any > > problems, please let me know. > > > > > > Best regards, > > Hans > Sorry, but I stopped doing any testing of the aardvark driver with the mainline kernel after PCI maintainers stopped taking fixes for the driver and stopped responding. I'm not going to debug same issues again, which I have analyzed, prepared fixes, sent patches and see no progress there. Seems that there is a status quo, and I'm not going to change it.
On Wed, May 07, 2025 at 06:36:20PM +0200, Pali Rohár wrote: > On Wednesday 07 May 2025 23:06:51 Hans Zhang wrote: > > On 2025/5/7 23:03, Hans Zhang wrote: > > > On 2025/5/7 01:41, Pali Rohár wrote: > > > > On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: > > > > > The Aardvark PCIe controller enforces a fixed 512B payload size via > > > > > PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe > > > > > core negotiations. > > > > > > > > > > Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and > > > > > PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core > > > > > during device initialization, leveraging root port configurations and > > > > > device-specific capabilities. > > > > > > > > > > Aligning Aardvark with the unified MPS framework ensures consistency, > > > > > avoids artificial constraints, and allows the hardware to operate at > > > > > its maximum supported payload size while adhering to PCIe > > > > > specifications. > > > > > > > > > > Signed-off-by: Hans Zhang <18255117159@163.com> > > > > > --- > > > > > drivers/pci/controller/pci-aardvark.c | 2 -- > > > > > 1 file changed, 2 deletions(-) > > > > > > > > > > diff --git a/drivers/pci/controller/pci-aardvark.c > > > > > b/drivers/pci/controller/pci-aardvark.c > > > > > index a29796cce420..d8852892994a 100644 > > > > > --- a/drivers/pci/controller/pci-aardvark.c > > > > > +++ b/drivers/pci/controller/pci-aardvark.c > > > > > @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct > > > > > advk_pcie *pcie) > > > > > reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > > reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > > > > > reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > > > > > - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; > > > > > reg &= ~PCI_EXP_DEVCTL_READRQ; > > > > > - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; > > > > > reg |= PCI_EXP_DEVCTL_READRQ_512B; > > > > > advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > > -- > > > > > 2.25.1 > > > > > > > > > > > > > Please do not remove this code. It is required part of the > > > > initialization of the aardvark PCI controller at the specific phase, > > > > as defined in the Armada 3700 Functional Specification. > > > > > > > > There were reported more issues with those Armada PCIe controllers for > > > > which were already sent patches to mailing list in last 5 years. But > > > > unfortunately not all fixes were taken / applied yet. > > > > > > Hi Pali, > > > > > > I replied to you in version v2. > > > > > > Is the maximum MPS supported by Armada 3700 512 bytes? > > IIRC yes, 512-byte mode is supported. And I think in past I was testing > some PCIe endpoint card which required 512-byte long payload and did not > worked in 256-byte long mode (not sure if the card was not able to split > transaction or something other was broken, it is quite longer time). > > > > What are the default values of DevCap.MPS and DevCtl.MPS? > > Do you mean values in the PCI-to-PCI bridge device of PCIe Root Port > type? > > Aardvark controller does not have the real HW PCI-to-PCI bridge device. > There is only in-kernel emulation drivers/pci/pci-bridge-emul.c which > create fake kernel PCI device in the hierarchy to make kernel and > userspace happy. Yes, this is deviation from the PCIe standard but well, > buggy HW is also HW. > > And same applies for the pci-mvebu.c driver for older Marvell PCIe HW. > Oh. Then this patch is not going to change the MPS setting of the root bus. But that also means that there is a deviation in what the PCI core expects for a root port and what is actually programmed in the hw. Even in this MPS case, if the PCI core decides to scale down the MPS value of the root port, then it won't be changed in the hw and the hw will continue to work with 512B? Shouldn't the controller driver change the hw values based on the values programmed by PCI core of the emul bridge? But until that is fixed, this patch should be dropped. - Mani -- மணிவண்ணன் சதாசிவம்
On Friday 09 May 2025 12:38:48 Manivannan Sadhasivam wrote: > On Wed, May 07, 2025 at 06:36:20PM +0200, Pali Rohár wrote: > > On Wednesday 07 May 2025 23:06:51 Hans Zhang wrote: > > > On 2025/5/7 23:03, Hans Zhang wrote: > > > > On 2025/5/7 01:41, Pali Rohár wrote: > > > > > On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: > > > > > > The Aardvark PCIe controller enforces a fixed 512B payload size via > > > > > > PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe > > > > > > core negotiations. > > > > > > > > > > > > Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and > > > > > > PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core > > > > > > during device initialization, leveraging root port configurations and > > > > > > device-specific capabilities. > > > > > > > > > > > > Aligning Aardvark with the unified MPS framework ensures consistency, > > > > > > avoids artificial constraints, and allows the hardware to operate at > > > > > > its maximum supported payload size while adhering to PCIe > > > > > > specifications. > > > > > > > > > > > > Signed-off-by: Hans Zhang <18255117159@163.com> > > > > > > --- > > > > > > drivers/pci/controller/pci-aardvark.c | 2 -- > > > > > > 1 file changed, 2 deletions(-) > > > > > > > > > > > > diff --git a/drivers/pci/controller/pci-aardvark.c > > > > > > b/drivers/pci/controller/pci-aardvark.c > > > > > > index a29796cce420..d8852892994a 100644 > > > > > > --- a/drivers/pci/controller/pci-aardvark.c > > > > > > +++ b/drivers/pci/controller/pci-aardvark.c > > > > > > @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct > > > > > > advk_pcie *pcie) > > > > > > reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > > > reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > > > > > > reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > > > > > > - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; > > > > > > reg &= ~PCI_EXP_DEVCTL_READRQ; > > > > > > - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; > > > > > > reg |= PCI_EXP_DEVCTL_READRQ_512B; > > > > > > advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > > > -- > > > > > > 2.25.1 > > > > > > > > > > > > > > > > Please do not remove this code. It is required part of the > > > > > initialization of the aardvark PCI controller at the specific phase, > > > > > as defined in the Armada 3700 Functional Specification. > > > > > > > > > > There were reported more issues with those Armada PCIe controllers for > > > > > which were already sent patches to mailing list in last 5 years. But > > > > > unfortunately not all fixes were taken / applied yet. > > > > > > > > Hi Pali, > > > > > > > > I replied to you in version v2. > > > > > > > > Is the maximum MPS supported by Armada 3700 512 bytes? > > > > IIRC yes, 512-byte mode is supported. And I think in past I was testing > > some PCIe endpoint card which required 512-byte long payload and did not > > worked in 256-byte long mode (not sure if the card was not able to split > > transaction or something other was broken, it is quite longer time). > > > > > > What are the default values of DevCap.MPS and DevCtl.MPS? > > > > Do you mean values in the PCI-to-PCI bridge device of PCIe Root Port > > type? > > > > Aardvark controller does not have the real HW PCI-to-PCI bridge device. > > There is only in-kernel emulation drivers/pci/pci-bridge-emul.c which > > create fake kernel PCI device in the hierarchy to make kernel and > > userspace happy. Yes, this is deviation from the PCIe standard but well, > > buggy HW is also HW. > > > > And same applies for the pci-mvebu.c driver for older Marvell PCIe HW. > > > > Oh. Then this patch is not going to change the MPS setting of the root bus. But > that also means that there is a deviation in what the PCI core expects for a > root port and what is actually programmed in the hw. Yes, exactly this aardvark PCIe controller deviates from the PCIe spec in lot of things. That is why it is needed to be really careful about such changes. Same applies for pci-mvebu.c. Both are PCIe controllers on Marvell hardware, but it questionable from who both these IPs and hence source of the issues. Also these PCIe controllers have lot of HW bugs and documented and undocumented erratas (for things which should work, but does not). So it is not just as "enable or disable this bit and it would work". It is needed to properly check if such functionality is provided by HW and whether there is not some documented/undocumented errata for this feature which could say "its broken, do not try to set this bit". > Even in this MPS case, if the PCI core decides to scale down the MPS value of > the root port, then it won't be changed in the hw and the hw will continue to > work with 512B? Shouldn't the controller driver change the hw values based on > the values programmed by PCI core of the emul bridge? Marvell PCIe controllers has their own ways how to configure different things of PCIe HW via custom platform registers. This is something which needs to be properly understood and implemented as 1:1 mapping to kernel root port emulator. Drivers should do it but it is unfinished. And as I already said I stopped any development in this area years ago when PCIe maintainers stopped taking my fixes for these drivers. As I said I'm not going to spend my free time to investigate again issues there, prepare fixes for them and just let them dropped into trash as nobody is interested in them. I have other more useful things to do in my free time. > But until that is fixed, this patch should be dropped.
On Fri, May 09, 2025 at 06:00:25PM +0200, Pali Rohár wrote: > On Friday 09 May 2025 12:38:48 Manivannan Sadhasivam wrote: > > On Wed, May 07, 2025 at 06:36:20PM +0200, Pali Rohár wrote: > > > On Wednesday 07 May 2025 23:06:51 Hans Zhang wrote: > > > > On 2025/5/7 23:03, Hans Zhang wrote: > > > > > On 2025/5/7 01:41, Pali Rohár wrote: > > > > > > On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: > > > > > > > The Aardvark PCIe controller enforces a fixed 512B payload size via > > > > > > > PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe > > > > > > > core negotiations. > > > > > > > > > > > > > > Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and > > > > > > > PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core > > > > > > > during device initialization, leveraging root port configurations and > > > > > > > device-specific capabilities. > > > > > > > > > > > > > > Aligning Aardvark with the unified MPS framework ensures consistency, > > > > > > > avoids artificial constraints, and allows the hardware to operate at > > > > > > > its maximum supported payload size while adhering to PCIe > > > > > > > specifications. > > > > > > > > > > > > > > Signed-off-by: Hans Zhang <18255117159@163.com> > > > > > > > --- > > > > > > > drivers/pci/controller/pci-aardvark.c | 2 -- > > > > > > > 1 file changed, 2 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/pci/controller/pci-aardvark.c > > > > > > > b/drivers/pci/controller/pci-aardvark.c > > > > > > > index a29796cce420..d8852892994a 100644 > > > > > > > --- a/drivers/pci/controller/pci-aardvark.c > > > > > > > +++ b/drivers/pci/controller/pci-aardvark.c > > > > > > > @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct > > > > > > > advk_pcie *pcie) > > > > > > > reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > > > > reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > > > > > > > reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > > > > > > > - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; > > > > > > > reg &= ~PCI_EXP_DEVCTL_READRQ; > > > > > > > - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; > > > > > > > reg |= PCI_EXP_DEVCTL_READRQ_512B; > > > > > > > advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > > > > > > > -- > > > > > > > 2.25.1 > > > > > > > > > > > > > > > > > > > Please do not remove this code. It is required part of the > > > > > > initialization of the aardvark PCI controller at the specific phase, > > > > > > as defined in the Armada 3700 Functional Specification. > > > > > > > > > > > > There were reported more issues with those Armada PCIe controllers for > > > > > > which were already sent patches to mailing list in last 5 years. But > > > > > > unfortunately not all fixes were taken / applied yet. > > > > > > > > > > Hi Pali, > > > > > > > > > > I replied to you in version v2. > > > > > > > > > > Is the maximum MPS supported by Armada 3700 512 bytes? > > > > > > IIRC yes, 512-byte mode is supported. And I think in past I was testing > > > some PCIe endpoint card which required 512-byte long payload and did not > > > worked in 256-byte long mode (not sure if the card was not able to split > > > transaction or something other was broken, it is quite longer time). > > > > > > > > What are the default values of DevCap.MPS and DevCtl.MPS? > > > > > > Do you mean values in the PCI-to-PCI bridge device of PCIe Root Port > > > type? > > > > > > Aardvark controller does not have the real HW PCI-to-PCI bridge device. > > > There is only in-kernel emulation drivers/pci/pci-bridge-emul.c which > > > create fake kernel PCI device in the hierarchy to make kernel and > > > userspace happy. Yes, this is deviation from the PCIe standard but well, > > > buggy HW is also HW. > > > > > > And same applies for the pci-mvebu.c driver for older Marvell PCIe HW. > > > > > > > Oh. Then this patch is not going to change the MPS setting of the root bus. But > > that also means that there is a deviation in what the PCI core expects for a > > root port and what is actually programmed in the hw. > > Yes, exactly this aardvark PCIe controller deviates from the PCIe spec > in lot of things. That is why it is needed to be really careful about > such changes. > > Same applies for pci-mvebu.c. Both are PCIe controllers on Marvell > hardware, but it questionable from who both these IPs and hence source > of the issues. > > Also these PCIe controllers have lot of HW bugs and documented and > undocumented erratas (for things which should work, but does not). > > So it is not just as "enable or disable this bit and it would work". It > is needed to properly check if such functionality is provided by HW and > whether there is not some documented/undocumented errata for this > feature which could say "its broken, do not try to set this bit". > > > Even in this MPS case, if the PCI core decides to scale down the MPS value of > > the root port, then it won't be changed in the hw and the hw will continue to > > work with 512B? Shouldn't the controller driver change the hw values based on > > the values programmed by PCI core of the emul bridge? > > Marvell PCIe controllers has their own ways how to configure different > things of PCIe HW via custom platform registers. This is something which > needs to be properly understood and implemented as 1:1 mapping to kernel > root port emulator. Drivers should do it but it is unfinished. And as I > already said I stopped any development in this area years ago when PCIe > maintainers stopped taking my fixes for these drivers. As I said I'm not > going to spend my free time to investigate again issues there, prepare > fixes for them and just let them dropped into trash as nobody is > interested in them. I have other more useful things to do in my free > time. > If the patches are not related to unloading the driver which acts as a msi controller, I don't see issues with them ;) But I have no visibility on the past conversations. - Mani -- மணிவண்ணன் சதாசிவம்
On 2025/5/9 15:08, Manivannan Sadhasivam wrote: > On Wed, May 07, 2025 at 06:36:20PM +0200, Pali Rohár wrote: >> On Wednesday 07 May 2025 23:06:51 Hans Zhang wrote: >>> On 2025/5/7 23:03, Hans Zhang wrote: >>>> On 2025/5/7 01:41, Pali Rohár wrote: >>>>> On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: >>>>>> The Aardvark PCIe controller enforces a fixed 512B payload size via >>>>>> PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe >>>>>> core negotiations. >>>>>> >>>>>> Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and >>>>>> PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core >>>>>> during device initialization, leveraging root port configurations and >>>>>> device-specific capabilities. >>>>>> >>>>>> Aligning Aardvark with the unified MPS framework ensures consistency, >>>>>> avoids artificial constraints, and allows the hardware to operate at >>>>>> its maximum supported payload size while adhering to PCIe >>>>>> specifications. >>>>>> >>>>>> Signed-off-by: Hans Zhang <18255117159@163.com> >>>>>> --- >>>>>> drivers/pci/controller/pci-aardvark.c | 2 -- >>>>>> 1 file changed, 2 deletions(-) >>>>>> >>>>>> diff --git a/drivers/pci/controller/pci-aardvark.c >>>>>> b/drivers/pci/controller/pci-aardvark.c >>>>>> index a29796cce420..d8852892994a 100644 >>>>>> --- a/drivers/pci/controller/pci-aardvark.c >>>>>> +++ b/drivers/pci/controller/pci-aardvark.c >>>>>> @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct >>>>>> advk_pcie *pcie) >>>>>> reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >>>>>> reg &= ~PCI_EXP_DEVCTL_RELAX_EN; >>>>>> reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; >>>>>> - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; >>>>>> reg &= ~PCI_EXP_DEVCTL_READRQ; >>>>>> - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; >>>>>> reg |= PCI_EXP_DEVCTL_READRQ_512B; >>>>>> advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >>>>>> -- >>>>>> 2.25.1 >>>>>> >>>>> >>>>> Please do not remove this code. It is required part of the >>>>> initialization of the aardvark PCI controller at the specific phase, >>>>> as defined in the Armada 3700 Functional Specification. >>>>> >>>>> There were reported more issues with those Armada PCIe controllers for >>>>> which were already sent patches to mailing list in last 5 years. But >>>>> unfortunately not all fixes were taken / applied yet. >>>> >>>> Hi Pali, >>>> >>>> I replied to you in version v2. >>>> >>>> Is the maximum MPS supported by Armada 3700 512 bytes? >> >> IIRC yes, 512-byte mode is supported. And I think in past I was testing >> some PCIe endpoint card which required 512-byte long payload and did not >> worked in 256-byte long mode (not sure if the card was not able to split >> transaction or something other was broken, it is quite longer time). >> >>>> What are the default values of DevCap.MPS and DevCtl.MPS? >> >> Do you mean values in the PCI-to-PCI bridge device of PCIe Root Port >> type? >> >> Aardvark controller does not have the real HW PCI-to-PCI bridge device. >> There is only in-kernel emulation drivers/pci/pci-bridge-emul.c which >> create fake kernel PCI device in the hierarchy to make kernel and >> userspace happy. Yes, this is deviation from the PCIe standard but well, >> buggy HW is also HW. >> >> And same applies for the pci-mvebu.c driver for older Marvell PCIe HW. >> > > Oh. Then this patch is not going to change the MPS setting of the root bus. But > that also means that there is a deviation in what the PCI core expects for a > root port and what is actually programmed in the hw. > > Even in this MPS case, if the PCI core decides to scale down the MPS value of > the root port, then it won't be changed in the hw and the hw will continue to > work with 512B? Shouldn't the controller driver change the hw values based on > the values programmed by PCI core of the emul bridge? > > But until that is fixed, this patch should be dropped. > Dear Mani, I will drop this patch in the next version. Best regards, Hans
On 2025/5/8 00:36, Pali Rohár wrote: > On Wednesday 07 May 2025 23:06:51 Hans Zhang wrote: >> On 2025/5/7 23:03, Hans Zhang wrote: >>> On 2025/5/7 01:41, Pali Rohár wrote: >>>> On Wednesday 07 May 2025 01:34:39 Hans Zhang wrote: >>>>> The Aardvark PCIe controller enforces a fixed 512B payload size via >>>>> PCI_EXP_DEVCTL_PAYLOAD_512B, overriding hardware capabilities and PCIe >>>>> core negotiations. >>>>> >>>>> Remove explicit MPS overrides (PCI_EXP_DEVCTL_PAYLOAD and >>>>> PCI_EXP_DEVCTL_PAYLOAD_512B). MPS is now determined by the PCI core >>>>> during device initialization, leveraging root port configurations and >>>>> device-specific capabilities. >>>>> >>>>> Aligning Aardvark with the unified MPS framework ensures consistency, >>>>> avoids artificial constraints, and allows the hardware to operate at >>>>> its maximum supported payload size while adhering to PCIe >>>>> specifications. >>>>> >>>>> Signed-off-by: Hans Zhang <18255117159@163.com> >>>>> --- >>>>> drivers/pci/controller/pci-aardvark.c | 2 -- >>>>> 1 file changed, 2 deletions(-) >>>>> >>>>> diff --git a/drivers/pci/controller/pci-aardvark.c >>>>> b/drivers/pci/controller/pci-aardvark.c >>>>> index a29796cce420..d8852892994a 100644 >>>>> --- a/drivers/pci/controller/pci-aardvark.c >>>>> +++ b/drivers/pci/controller/pci-aardvark.c >>>>> @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct >>>>> advk_pcie *pcie) >>>>> reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >>>>> reg &= ~PCI_EXP_DEVCTL_RELAX_EN; >>>>> reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; >>>>> - reg &= ~PCI_EXP_DEVCTL_PAYLOAD; >>>>> reg &= ~PCI_EXP_DEVCTL_READRQ; >>>>> - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; >>>>> reg |= PCI_EXP_DEVCTL_READRQ_512B; >>>>> advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); >>>>> -- >>>>> 2.25.1 >>>>> >>>> >>>> Please do not remove this code. It is required part of the >>>> initialization of the aardvark PCI controller at the specific phase, >>>> as defined in the Armada 3700 Functional Specification. >>>> >>>> There were reported more issues with those Armada PCIe controllers for >>>> which were already sent patches to mailing list in last 5 years. But >>>> unfortunately not all fixes were taken / applied yet. >>> >>> Hi Pali, >>> >>> I replied to you in version v2. >>> >>> Is the maximum MPS supported by Armada 3700 512 bytes? > > IIRC yes, 512-byte mode is supported. And I think in past I was testing > some PCIe endpoint card which required 512-byte long payload and did not > worked in 256-byte long mode (not sure if the card was not able to split > transaction or something other was broken, it is quite longer time). > >>> What are the default values of DevCap.MPS and DevCtl.MPS? > > Do you mean values in the PCI-to-PCI bridge device of PCIe Root Port > type? > > Aardvark controller does not have the real HW PCI-to-PCI bridge device. > There is only in-kernel emulation drivers/pci/pci-bridge-emul.c which > create fake kernel PCI device in the hierarchy to make kernel and > userspace happy. Yes, this is deviation from the PCIe standard but well, > buggy HW is also HW. > > And same applies for the pci-mvebu.c driver for older Marvell PCIe HW. > >>> Because the default value of DevCtl.MPS is not 512 bytes, it needs to be >>> configured here, right? >>> >>> If it's my guess, RK3588 also has the same requirements as you, just >>> like the first patch I submitted. >>> >>> Please take a look at the communication history: >>> https://patchwork.kernel.org/project/linux-pci/patch/20250416151926.140202-1-18255117159@163.com/ >> And this: >> https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-2-18255117159@163.com/ > > These changes are referring the to root ports PCI devices, which are not > applicable for aardvark PCIe controller. > >>> >>> Please test it using patch 1/3 of this series. If there are any >>> problems, please let me know. >>> >>> >>> Best regards, >>> Hans >> > > Sorry, but I stopped doing any testing of the aardvark driver with the > mainline kernel after PCI maintainers stopped taking fixes for the > driver and stopped responding. > > I'm not going to debug same issues again, which I have analyzed, > prepared fixes, sent patches and see no progress there. > > Seems that there is a status quo, and I'm not going to change it. Dear Niklas, Do you have any opinion on Pali's reply? Should patch 3/3 be discarded? Beat regards, Hans
Hello Hans, On Thu, May 08, 2025 at 12:47:12AM +0800, Hans Zhang wrote: > On 2025/5/8 00:36, Pali Rohár wrote: > > > > Sorry, but I stopped doing any testing of the aardvark driver with the > > mainline kernel after PCI maintainers stopped taking fixes for the > > driver and stopped responding. > > > > I'm not going to debug same issues again, which I have analyzed, > > prepared fixes, sent patches and see no progress there. > > > > Seems that there is a status quo, and I'm not going to change it. > > Dear Niklas, > > Do you have any opinion on Pali's reply? Should patch 3/3 be discarded? While I do have an opinion, I'm not going to share it on a public mailing list :) With regards to your patch 3/3, I think that your patch looks fine, but if the driver maintainer does not want the cleanup for >reasons*, that is totally fine with me. However, I'm not a PCI maintainer, so my opinion does not really matter. It's the PCI maintainers that decide. Kind regards, Niklas
On 2025/5/8 19:53, Niklas Cassel wrote: > Hello Hans, > > On Thu, May 08, 2025 at 12:47:12AM +0800, Hans Zhang wrote: >> On 2025/5/8 00:36, Pali Rohár wrote: >>> >>> Sorry, but I stopped doing any testing of the aardvark driver with the >>> mainline kernel after PCI maintainers stopped taking fixes for the >>> driver and stopped responding. >>> >>> I'm not going to debug same issues again, which I have analyzed, >>> prepared fixes, sent patches and see no progress there. >>> >>> Seems that there is a status quo, and I'm not going to change it. >> >> Dear Niklas, >> >> Do you have any opinion on Pali's reply? Should patch 3/3 be discarded? > > While I do have an opinion, I'm not going to share it on a public mailing > list :) > > With regards to your patch 3/3, I think that your patch looks fine, but if > the driver maintainer does not want the cleanup for >reasons*, that is totally > fine with me. However, I'm not a PCI maintainer, so my opinion does not really > matter. It's the PCI maintainers that decide. > Dear Niklas, Thank you very much for your reply. Let's wait for the decision of the PCI maintainer on this series of patches. Best regards, Hans
On Friday 09 May 2025 00:12:24 Hans Zhang wrote: > On 2025/5/8 19:53, Niklas Cassel wrote: > > Hello Hans, > > > > On Thu, May 08, 2025 at 12:47:12AM +0800, Hans Zhang wrote: > > > On 2025/5/8 00:36, Pali Rohár wrote: > > > > > > > > Sorry, but I stopped doing any testing of the aardvark driver with the > > > > mainline kernel after PCI maintainers stopped taking fixes for the > > > > driver and stopped responding. > > > > > > > > I'm not going to debug same issues again, which I have analyzed, > > > > prepared fixes, sent patches and see no progress there. > > > > > > > > Seems that there is a status quo, and I'm not going to change it. > > > > > > Dear Niklas, > > > > > > Do you have any opinion on Pali's reply? Should patch 3/3 be discarded? > > > > While I do have an opinion, I'm not going to share it on a public mailing > > list :) > > > > With regards to your patch 3/3, I think that your patch looks fine, but if > > the driver maintainer does not want the cleanup for >reasons*, that is totally > > fine with me. However, I'm not a PCI maintainer, so my opinion does not really > > matter. It's the PCI maintainers that decide. > > > > Dear Niklas, > > Thank you very much for your reply. Let's wait for the decision of the PCI > maintainer on this series of patches. > > Best regards, > Hans > I do not see any cleanup in 3/3. There is just a removal of the step needed for configuring the controller.
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