[PATCH v3 0/3] RISC-V KVM selftests improvements

Atish Patra posted 3 patches 7 months, 2 weeks ago
.../selftests/kvm/include/riscv/processor.h        |  23 +++-
tools/testing/selftests/kvm/lib/riscv/handlers.S   | 139 +++++++++++----------
tools/testing/selftests/kvm/lib/riscv/processor.c  |   2 +-
tools/testing/selftests/kvm/riscv/arch_timer.c     |   2 +-
tools/testing/selftests/kvm/riscv/ebreak_test.c    |   2 +-
tools/testing/selftests/kvm/riscv/get-reg-list.c   | 132 +++++++++++++++++++
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c   |  24 +++-
7 files changed, 247 insertions(+), 77 deletions(-)
[PATCH v3 0/3] RISC-V KVM selftests improvements
Posted by Atish Patra 7 months, 2 weeks ago
This series improves the following tests.
1. Get-reg-list : Adds vector support
2. SBI PMU test : Distinguish between different types of illegal exception

The first patch is just helper patch that adds stval support during
exception handling.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Changes in v3:
- Dropped the redundant macros and rv32 specific csr details. 
- Changed to vcpu_get_reg from __vcpu_get_reg based on suggestion from Drew.
- Added RB tags from Drew.
- Link to v2: https://lore.kernel.org/r/20250429-kvm_selftest_improve-v2-0-51713f91e04a@rivosinc.com

Changes in v2:
- Rebased on top of Linux 6.15-rc4
- Changed from ex_regs to pt_regs based on Drew's suggestion. 
- Dropped Anup's review on PATCH1 as it is significantly changed from last review.
- Moved the instruction decoding macros to a common header file.
- Improved the vector reg list test as per the feedback.
- Link to v1: https://lore.kernel.org/r/20250324-kvm_selftest_improve-v1-0-583620219d4f@rivosinc.com

---
Atish Patra (3):
      KVM: riscv: selftests: Align the trap information wiht pt_regs
      KVM: riscv: selftests: Decode stval to identify exact exception type
      KVM: riscv: selftests: Add vector extension tests

 .../selftests/kvm/include/riscv/processor.h        |  23 +++-
 tools/testing/selftests/kvm/lib/riscv/handlers.S   | 139 +++++++++++----------
 tools/testing/selftests/kvm/lib/riscv/processor.c  |   2 +-
 tools/testing/selftests/kvm/riscv/arch_timer.c     |   2 +-
 tools/testing/selftests/kvm/riscv/ebreak_test.c    |   2 +-
 tools/testing/selftests/kvm/riscv/get-reg-list.c   | 132 +++++++++++++++++++
 tools/testing/selftests/kvm/riscv/sbi_pmu_test.c   |  24 +++-
 7 files changed, 247 insertions(+), 77 deletions(-)
---
base-commit: f15d97df5afae16f40ecef942031235d1c6ba14f
change-id: 20250324-kvm_selftest_improve-9bedb9f0a6d3
--
Regards,
Atish patra
Re: [PATCH v3 0/3] RISC-V KVM selftests improvements
Posted by Anup Patel 7 months, 2 weeks ago
On Wed, Apr 30, 2025 at 1:46 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> This series improves the following tests.
> 1. Get-reg-list : Adds vector support
> 2. SBI PMU test : Distinguish between different types of illegal exception
>
> The first patch is just helper patch that adds stval support during
> exception handling.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Changes in v3:
> - Dropped the redundant macros and rv32 specific csr details.
> - Changed to vcpu_get_reg from __vcpu_get_reg based on suggestion from Drew.
> - Added RB tags from Drew.
> - Link to v2: https://lore.kernel.org/r/20250429-kvm_selftest_improve-v2-0-51713f91e04a@rivosinc.com
>
> Changes in v2:
> - Rebased on top of Linux 6.15-rc4
> - Changed from ex_regs to pt_regs based on Drew's suggestion.
> - Dropped Anup's review on PATCH1 as it is significantly changed from last review.
> - Moved the instruction decoding macros to a common header file.
> - Improved the vector reg list test as per the feedback.
> - Link to v1: https://lore.kernel.org/r/20250324-kvm_selftest_improve-v1-0-583620219d4f@rivosinc.com
>
> ---
> Atish Patra (3):
>       KVM: riscv: selftests: Align the trap information wiht pt_regs
>       KVM: riscv: selftests: Decode stval to identify exact exception type
>       KVM: riscv: selftests: Add vector extension tests

Queued this series for Linux-6.16.

Thanks,
Anup