Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
masks and shifts and make the code a bit more readable.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v5:
1. New patch
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++++++---
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++-
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index ca1a120f630a3650bf6d9f9d426cccea88c22e7f..7ef0aa7ff41b7d10d2630405c3d2f541957f19ea 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -362,17 +362,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
{
u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
- writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
ndelay(250);
}
static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
{
u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+ data |= DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
+ writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
- writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
ndelay(250);
}
@@ -996,7 +998,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
}
/* de-assert digital and pll power down */
- data = BIT(6) | BIT(5);
+ data = DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B |
+ DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
/* Assert PLL core reset */
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
index d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367..d49122b88d14896ef3e87b783a1691f85b61aa9c 100644
--- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
@@ -22,7 +22,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<reg32 offset="0x00018" name="GLBL_CTRL"/>
<reg32 offset="0x0001c" name="RBUF_CTRL"/>
<reg32 offset="0x00020" name="VREG_CTRL_0"/>
- <reg32 offset="0x00024" name="CTRL_0"/>
+ <reg32 offset="0x00024" name="CTRL_0">
+ <bitfield name="CLKSL_SHUTDOWNB" pos="7" type="boolean"/>
+ <bitfield name="DIGTOP_PWRDN_B" pos="6" type="boolean"/>
+ <bitfield name="PLL_SHUTDOWNB" pos="5" type="boolean"/>
+ <bitfield name="DLN3_SHUTDOWNB" pos="4" type="boolean"/>
+ <bitfield name="DLN2_SHUTDOWNB" pos="3" type="boolean"/>
+ <bitfield name="CLK_SHUTDOWNB" pos="2" type="boolean"/>
+ <bitfield name="DLN1_SHUTDOWNB" pos="1" type="boolean"/>
+ <bitfield name="DLN0_SHUTDOWNB" pos="0" type="boolean"/>
+ </reg32>
<reg32 offset="0x00028" name="CTRL_1"/>
<reg32 offset="0x0002c" name="CTRL_2"/>
<reg32 offset="0x00030" name="CTRL_3"/>
--
2.45.2On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
> masks and shifts and make the code a bit more readable.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Changes in v5:
> 1. New patch
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++++++---
> drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++-
> 2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index ca1a120f630a3650bf6d9f9d426cccea88c22e7f..7ef0aa7ff41b7d10d2630405c3d2f541957f19ea 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -362,17 +362,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
> {
> u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
This (and several following functions) should be triggering a warning
regarding empty line after variable declaration block.
> + data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
>
> writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
> - writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> ndelay(250);
> }
>
> static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
> {
> u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> + data |= DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
> + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> - writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
> ndelay(250);
> }
> @@ -996,7 +998,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> }
>
> /* de-assert digital and pll power down */
> - data = BIT(6) | BIT(5);
> + data = DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B |
> + DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
> writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> /* Assert PLL core reset */
> diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
> index d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367..d49122b88d14896ef3e87b783a1691f85b61aa9c 100644
> --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
> +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
> @@ -22,7 +22,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
> <reg32 offset="0x00018" name="GLBL_CTRL"/>
> <reg32 offset="0x0001c" name="RBUF_CTRL"/>
> <reg32 offset="0x00020" name="VREG_CTRL_0"/>
> - <reg32 offset="0x00024" name="CTRL_0"/>
> + <reg32 offset="0x00024" name="CTRL_0">
> + <bitfield name="CLKSL_SHUTDOWNB" pos="7" type="boolean"/>
> + <bitfield name="DIGTOP_PWRDN_B" pos="6" type="boolean"/>
> + <bitfield name="PLL_SHUTDOWNB" pos="5" type="boolean"/>
> + <bitfield name="DLN3_SHUTDOWNB" pos="4" type="boolean"/>
> + <bitfield name="DLN2_SHUTDOWNB" pos="3" type="boolean"/>
> + <bitfield name="CLK_SHUTDOWNB" pos="2" type="boolean"/>
> + <bitfield name="DLN1_SHUTDOWNB" pos="1" type="boolean"/>
> + <bitfield name="DLN0_SHUTDOWNB" pos="0" type="boolean"/>
> + </reg32>
> <reg32 offset="0x00028" name="CTRL_1"/>
> <reg32 offset="0x0002c" name="CTRL_2"/>
> <reg32 offset="0x00030" name="CTRL_3"/>
>
> --
> 2.45.2
>
--
With best wishes
Dmitry
On 03/05/2025 00:44, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
>> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
>> masks and shifts and make the code a bit more readable.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>>
>> Changes in v5:
>> 1. New patch
>> ---
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++++++---
>> drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++-
>> 2 files changed, 16 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index ca1a120f630a3650bf6d9f9d426cccea88c22e7f..7ef0aa7ff41b7d10d2630405c3d2f541957f19ea 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -362,17 +362,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
>> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
>> {
>> u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> This (and several following functions) should be triggering a warning
> regarding empty line after variable declaration block.
Hey Dmitry,
I am implementing all the feedback and probably rebasing but to clarify
this part:
There is no checkpatch --strict warning here exactly for the reason I
was saying. For readability there should be no empty line after because
such statements are expected to be together. I don't mind of course
adding one, so I will implement the change.
Best regards,
Krzysztof
On Tue, May 20, 2025 at 12:57:25PM +0200, Krzysztof Kozlowski wrote:
> On 03/05/2025 00:44, Dmitry Baryshkov wrote:
> > On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
> >> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
> >> masks and shifts and make the code a bit more readable.
> >>
> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >>
> >> ---
> >>
> >> Changes in v5:
> >> 1. New patch
> >> ---
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++++++---
> >> drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++-
> >> 2 files changed, 16 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> index ca1a120f630a3650bf6d9f9d426cccea88c22e7f..7ef0aa7ff41b7d10d2630405c3d2f541957f19ea 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> @@ -362,17 +362,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
> >> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
> >> {
> >> u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
> >
> > This (and several following functions) should be triggering a warning
> > regarding empty line after variable declaration block.
>
> Hey Dmitry,
>
> I am implementing all the feedback and probably rebasing but to clarify
> this part:
>
> There is no checkpatch --strict warning here exactly for the reason I
> was saying. For readability there should be no empty line after because
> such statements are expected to be together. I don't mind of course
> adding one, so I will implement the change.
I'd prefer this:
u32 data;
data = readl();
data &= foo;;
>
>
> Best regards,
> Krzysztof
--
With best wishes
Dmitry
On 20/05/2025 23:23, Dmitry Baryshkov wrote: >> >> There is no checkpatch --strict warning here exactly for the reason I >> was saying. For readability there should be no empty line after because >> such statements are expected to be together. I don't mind of course >> adding one, so I will implement the change. > > I'd prefer this: > > u32 data; > > data = readl(); > data &= foo;; Ah, ok, I understand now. Best regards, Krzysztof
On 03/05/2025 00:44, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
>> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
>> masks and shifts and make the code a bit more readable.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>>
>> Changes in v5:
>> 1. New patch
>> ---
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++++++---
>> drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++-
>> 2 files changed, 16 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index ca1a120f630a3650bf6d9f9d426cccea88c22e7f..7ef0aa7ff41b7d10d2630405c3d2f541957f19ea 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -362,17 +362,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
>> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
>> {
>> u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> This (and several following functions) should be triggering a warning
> regarding empty line after variable declaration block.
You mean --strict or what? It is common to have the &= immediately after
assignment, so that's why I chosen that syntax. It is just more
readable, but I understand your comment that you want --strict
compliancen even if it hurts readability, so I'll change it.
Best regards,
Krzysztof
On 05/05/2025 09:17, Krzysztof Kozlowski wrote:
> On 03/05/2025 00:44, Dmitry Baryshkov wrote:
>> On Wed, Apr 30, 2025 at 03:00:45PM +0200, Krzysztof Kozlowski wrote:
>>> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
>>> masks and shifts and make the code a bit more readable.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>
>>> ---
>>>
>>> Changes in v5:
>>> 1. New patch
>>> ---
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 9 ++++++---
>>> drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++-
>>> 2 files changed, 16 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> index ca1a120f630a3650bf6d9f9d426cccea88c22e7f..7ef0aa7ff41b7d10d2630405c3d2f541957f19ea 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> @@ -362,17 +362,19 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
>>> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
>>> {
>>> u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>>
>> This (and several following functions) should be triggering a warning
>> regarding empty line after variable declaration block.
>
> You mean --strict or what? It is common to have the &= immediately after
> assignment, so that's why I chosen that syntax. It is just more
> readable, but I understand your comment that you want --strict
> compliancen even if it hurts readability, so I'll change it.
I'd probably prefer to split variable declaration and readl invocation.
Then the code will be logical with &= comining on the line adjacent to
readl().
>
>
>
> Best regards,
> Krzysztof
--
With best wishes
Dmitry
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