From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Introduce support for module clocks that may be sourced from an external
clock rather than the on-chip PLL. Add two new fields `external_clk` and
`external_clk_mux_index` to `struct rzv2h_mod_clk` and `struct mod_clock`
to mark such clocks and record the mux index corresponding to the external
input.
Provide a new helper macro `DEF_MOD_MUX_EXTERNAL()` for concise declaration
of external-source module clocks.
In `rzv2h_mod_clock_is_enabled()`, detect when the parent mux selects the
external source (by comparing the current mux index against
`external_clk_mux_index`) and skip the normal CLK_MON register check in
that case. Update `rzv2h_cpg_register_mod_clk()` to populate the new fields
from the SoC info.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
- Renamed helper macro to `DEF_MOD_MUX_EXTERNAL()`.
- Added a new field `external_clk_mux_index` to `struct mod_clock` to
store the mux index corresponding to the external input.
- Updated the `rzv2h_mod_clock_is_enabled()` function to check if the
parent mux selects the external source by comparing the current mux
index against `external_clk_mux_index`.
- Updated the `rzv2h_cpg_register_mod_clk()` function to populate the new
fields from the SoC info.
- Updated commit description
v1->v2:
- None
---
drivers/clk/renesas/rzv2h-cpg.c | 31 ++++++++++++++++++++++++++++++-
drivers/clk/renesas/rzv2h-cpg.h | 23 +++++++++++++++++++----
2 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index bcc496e8cbcd..e03c9801d2e9 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -119,6 +119,8 @@ struct pll_clk {
* @on_bit: ON/MON bit
* @mon_index: monitor register offset
* @mon_bit: monitor bit
+ * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
+ * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
*/
struct mod_clock {
struct rzv2h_cpg_priv *priv;
@@ -129,6 +131,8 @@ struct mod_clock {
u8 on_bit;
s8 mon_index;
u8 mon_bit;
+ bool external_clk;
+ u8 external_clk_mux_index;
};
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
@@ -567,10 +571,33 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
{
struct mod_clock *clock = to_mod_clock(hw);
struct rzv2h_cpg_priv *priv = clock->priv;
+ bool skip_mon = false;
u32 bitmask;
u32 offset;
- if (clock->mon_index >= 0) {
+ if (clock->mon_index >= 0 && clock->external_clk) {
+ struct clk_hw *parent_hw;
+ struct clk *parent_clk;
+ struct clk_mux *mux;
+ int index;
+ u32 val;
+
+ parent_clk = clk_get_parent(hw->clk);
+ if (IS_ERR(parent_clk))
+ goto check_mon;
+
+ parent_hw = __clk_get_hw(parent_clk);
+ mux = to_clk_mux(parent_hw);
+
+ val = readl(mux->reg) >> mux->shift;
+ val &= mux->mask;
+ index = clk_mux_val_to_index(parent_hw, mux->table, 0, val);
+ if (index == clock->external_clk_mux_index)
+ skip_mon = true;
+ }
+
+check_mon:
+ if (clock->mon_index >= 0 && !skip_mon) {
offset = GET_CLK_MON_OFFSET(clock->mon_index);
bitmask = BIT(clock->mon_bit);
@@ -687,6 +714,8 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
clock->mon_index = mod->mon_index;
clock->mon_bit = mod->mon_bit;
clock->no_pm = mod->no_pm;
+ clock->external_clk = mod->external_clk;
+ clock->external_clk_mux_index = mod->external_clk_mux_index;
clock->priv = priv;
clock->hw.init = &init;
clock->mstop_data = mod->mstop_data;
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 449f8c82e8fb..687587033688 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -192,6 +192,8 @@ enum clk_types {
* @on_bit: ON bit
* @mon_index: monitor register index
* @mon_bit: monitor bit
+ * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
+ * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
*/
struct rzv2h_mod_clk {
const char *name;
@@ -203,9 +205,12 @@ struct rzv2h_mod_clk {
u8 on_bit;
s8 mon_index;
u8 mon_bit;
+ bool external_clk;
+ u8 external_clk_mux_index;
};
-#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
+#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
+ _onbit, _monindex, _monbit, _external_clk, _external_clk_mux_index) \
{ \
.name = (_name), \
.mstop_data = (_mstop), \
@@ -216,16 +221,26 @@ struct rzv2h_mod_clk {
.on_bit = (_onbit), \
.mon_index = (_monindex), \
.mon_bit = (_monbit), \
+ .external_clk = (_external_clk), \
+ .external_clk_mux_index = (_external_clk_mux_index), \
}
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
- DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
+ DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+ false, 0)
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
- DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
+ DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, \
+ false, 0)
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
- DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
+ DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, \
+ false, 0)
+
+#define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
+ _external_clk_mux_index) \
+ DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+ true, _external_clk_mux_index)
/**
* struct rzv2h_reset - Reset definitions
--
2.49.0Hi Prabhakar,
On Mon, 28 Apr 2025 at 20:42, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Introduce support for module clocks that may be sourced from an external
> clock rather than the on-chip PLL. Add two new fields `external_clk` and
> `external_clk_mux_index` to `struct rzv2h_mod_clk` and `struct mod_clock`
> to mark such clocks and record the mux index corresponding to the external
> input.
>
> Provide a new helper macro `DEF_MOD_MUX_EXTERNAL()` for concise declaration
> of external-source module clocks.
>
> In `rzv2h_mod_clock_is_enabled()`, detect when the parent mux selects the
> external source (by comparing the current mux index against
> `external_clk_mux_index`) and skip the normal CLK_MON register check in
> that case. Update `rzv2h_cpg_register_mod_clk()` to populate the new fields
> from the SoC info.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> - Renamed helper macro to `DEF_MOD_MUX_EXTERNAL()`.
> - Added a new field `external_clk_mux_index` to `struct mod_clock` to
> store the mux index corresponding to the external input.
> - Updated the `rzv2h_mod_clock_is_enabled()` function to check if the
> parent mux selects the external source by comparing the current mux
> index against `external_clk_mux_index`.
> - Updated the `rzv2h_cpg_register_mod_clk()` function to populate the new
> fields from the SoC info.
> - Updated commit description
Thanks for the update!
LGTM. But as I will not apply the second patch yet anyway, I am a
little bit more pedantic with my comments below (no offense intended,
though ;-)
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -119,6 +119,8 @@ struct pll_clk {
> * @on_bit: ON/MON bit
> * @mon_index: monitor register offset
> * @mon_bit: monitor bit
> + * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
> + * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
> */
> struct mod_clock {
> struct rzv2h_cpg_priv *priv;
> @@ -129,6 +131,8 @@ struct mod_clock {
> u8 on_bit;
> s8 mon_index;
> u8 mon_bit;
> + bool external_clk;
> + u8 external_clk_mux_index;
Perhaps combine these two fields into
s8 ext_clk_mux_index;
with -1 indicating not valid, cfr. mon_bit?
> };
>
> #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
> @@ -567,10 +571,33 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
> {
> struct mod_clock *clock = to_mod_clock(hw);
> struct rzv2h_cpg_priv *priv = clock->priv;
> + bool skip_mon = false;
> u32 bitmask;
> u32 offset;
>
> - if (clock->mon_index >= 0) {
> + if (clock->mon_index >= 0 && clock->external_clk) {
I think the first condition can be dropped, as clock->external_clk
implies a valid mon_index.
> + struct clk_hw *parent_hw;
> + struct clk *parent_clk;
> + struct clk_mux *mux;
> + int index;
> + u32 val;
> +
> + parent_clk = clk_get_parent(hw->clk);
> + if (IS_ERR(parent_clk))
Can this actually happen?
> + goto check_mon;
> +
> + parent_hw = __clk_get_hw(parent_clk);
> + mux = to_clk_mux(parent_hw);
> +
> + val = readl(mux->reg) >> mux->shift;
> + val &= mux->mask;
> + index = clk_mux_val_to_index(parent_hw, mux->table, 0, val);
> + if (index == clock->external_clk_mux_index)
> + skip_mon = true;
> + }
> +
> +check_mon:
> + if (clock->mon_index >= 0 && !skip_mon) {
> offset = GET_CLK_MON_OFFSET(clock->mon_index);
> bitmask = BIT(clock->mon_bit);
>
I am not so fond of the goto and the !skip_mon logic, and wonder
if we can improve? Perhaps spin of the index obtaining logic into a
parent_clk_mux_index() helper, and something like:
int mon_index = clock->mon_index;
if (clock->external_clk) {
if (parent_clk_mux_index(hw) == clock->external_clk_mux_index))
mon_index = -1;
}
if (mon_index >= 0) {
// do it
}
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -192,6 +192,8 @@ enum clk_types {
> * @on_bit: ON bit
> * @mon_index: monitor register index
> * @mon_bit: monitor bit
> + * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
> + * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
> */
> struct rzv2h_mod_clk {
> const char *name;
> @@ -203,9 +205,12 @@ struct rzv2h_mod_clk {
> u8 on_bit;
> s8 mon_index;
> u8 mon_bit;
> + bool external_clk;
> + u8 external_clk_mux_index;
s8 ext_clk_mux_index
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Thu, May 8, 2025 at 5:06 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 28 Apr 2025 at 20:42, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Introduce support for module clocks that may be sourced from an external
> > clock rather than the on-chip PLL. Add two new fields `external_clk` and
> > `external_clk_mux_index` to `struct rzv2h_mod_clk` and `struct mod_clock`
> > to mark such clocks and record the mux index corresponding to the external
> > input.
> >
> > Provide a new helper macro `DEF_MOD_MUX_EXTERNAL()` for concise declaration
> > of external-source module clocks.
> >
> > In `rzv2h_mod_clock_is_enabled()`, detect when the parent mux selects the
> > external source (by comparing the current mux index against
> > `external_clk_mux_index`) and skip the normal CLK_MON register check in
> > that case. Update `rzv2h_cpg_register_mod_clk()` to populate the new fields
> > from the SoC info.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3:
> > - Renamed helper macro to `DEF_MOD_MUX_EXTERNAL()`.
> > - Added a new field `external_clk_mux_index` to `struct mod_clock` to
> > store the mux index corresponding to the external input.
> > - Updated the `rzv2h_mod_clock_is_enabled()` function to check if the
> > parent mux selects the external source by comparing the current mux
> > index against `external_clk_mux_index`.
> > - Updated the `rzv2h_cpg_register_mod_clk()` function to populate the new
> > fields from the SoC info.
> > - Updated commit description
>
> Thanks for the update!
>
> LGTM. But as I will not apply the second patch yet anyway, I am a
> little bit more pedantic with my comments below (no offense intended,
> though ;-)
>
No offense taken at all, I appreciate the thoroughness. I'll make the
suggested adjustments :)
> > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
> > @@ -119,6 +119,8 @@ struct pll_clk {
> > * @on_bit: ON/MON bit
> > * @mon_index: monitor register offset
> > * @mon_bit: monitor bit
> > + * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
> > + * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
> > */
> > struct mod_clock {
> > struct rzv2h_cpg_priv *priv;
> > @@ -129,6 +131,8 @@ struct mod_clock {
> > u8 on_bit;
> > s8 mon_index;
> > u8 mon_bit;
> > + bool external_clk;
> > + u8 external_clk_mux_index;
>
> Perhaps combine these two fields into
>
> s8 ext_clk_mux_index;
>
> with -1 indicating not valid, cfr. mon_bit?
>
Good point.
>
> > };
> >
> > #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
> > @@ -567,10 +571,33 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
> > {
> > struct mod_clock *clock = to_mod_clock(hw);
> > struct rzv2h_cpg_priv *priv = clock->priv;
> > + bool skip_mon = false;
> > u32 bitmask;
> > u32 offset;
> >
> > - if (clock->mon_index >= 0) {
> > + if (clock->mon_index >= 0 && clock->external_clk) {
>
> I think the first condition can be dropped, as clock->external_clk
> implies a valid mon_index.
>
Agreed.
> > + struct clk_hw *parent_hw;
> > + struct clk *parent_clk;
> > + struct clk_mux *mux;
> > + int index;
> > + u32 val;
> > +
> > + parent_clk = clk_get_parent(hw->clk);
> > + if (IS_ERR(parent_clk))
>
> Can this actually happen?
>
No, I will drop this and add a comment.
> > + goto check_mon;
> > +
> > + parent_hw = __clk_get_hw(parent_clk);
> > + mux = to_clk_mux(parent_hw);
> > +
> > + val = readl(mux->reg) >> mux->shift;
> > + val &= mux->mask;
> > + index = clk_mux_val_to_index(parent_hw, mux->table, 0, val);
> > + if (index == clock->external_clk_mux_index)
> > + skip_mon = true;
> > + }
> > +
> > +check_mon:
> > + if (clock->mon_index >= 0 && !skip_mon) {
> > offset = GET_CLK_MON_OFFSET(clock->mon_index);
> > bitmask = BIT(clock->mon_bit);
> >
>
> I am not so fond of the goto and the !skip_mon logic, and wonder
> if we can improve? Perhaps spin of the index obtaining logic into a
> parent_clk_mux_index() helper, and something like:
>
Ok, I'll add a helper rzv2h_clk_mux_to_index().
> int mon_index = clock->mon_index;
>
> if (clock->external_clk) {
> if (parent_clk_mux_index(hw) == clock->external_clk_mux_index))
> mon_index = -1;
> }
>
> if (mon_index >= 0) {
> // do it
> }
>
Agreed, with this we can get rid of goto.
> > --- a/drivers/clk/renesas/rzv2h-cpg.h
> > +++ b/drivers/clk/renesas/rzv2h-cpg.h
> > @@ -192,6 +192,8 @@ enum clk_types {
> > * @on_bit: ON bit
> > * @mon_index: monitor register index
> > * @mon_bit: monitor bit
> > + * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
> > + * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
> > */
> > struct rzv2h_mod_clk {
> > const char *name;
> > @@ -203,9 +205,12 @@ struct rzv2h_mod_clk {
> > u8 on_bit;
> > s8 mon_index;
> > u8 mon_bit;
> > + bool external_clk;
> > + u8 external_clk_mux_index;
>
> s8 ext_clk_mux_index
>
OK.
Cheers,
Prabhakar
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