Hi Tomi,
Thanks for the patch.
On 4/25/2025 1:01 PM, Tomi Valkeinen wrote:
> Add support for Y8 and Y10_P32 formats. We also need to add new csc
> matrices for the y-only formats.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
> ---
> drivers/gpu/drm/xlnx/zynqmp_disp.c | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> index 1dc77f2e4262..fe111fa8cc13 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> @@ -307,6 +307,16 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
> .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
> .swap = false,
> .sf = scaling_factors_101010,
> + }, {
> + .drm_fmt = DRM_FORMAT_Y8,
> + .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO,
> + .swap = false,
> + .sf = scaling_factors_888,
> + }, {
> + .drm_fmt = DRM_FORMAT_Y10_P32,
> + .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10,
> + .swap = false,
> + .sf = scaling_factors_101010,
> },
> };
>
> @@ -697,6 +707,16 @@ static const u32 csc_sdtv_to_rgb_offsets[] = {
> 0x0, 0x1800, 0x1800
> };
>
> +static const u16 csc_sdtv_to_rgb_yonly_matrix[] = {
> + 0x0, 0x0, 0x1000,
> + 0x0, 0x0, 0x1000,
> + 0x0, 0x0, 0x1000,
> +};
> +
> +static const u32 csc_sdtv_to_rgb_yonly_offsets[] = {
> + 0x0, 0x0, 0x0
> +};
> +
> /**
> * zynqmp_disp_blend_set_output_format - Set the output format of the blender
> * @disp: Display controller
> @@ -846,7 +866,11 @@ static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
> ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
> val);
>
> - if (layer->drm_fmt->is_yuv) {
> + if (layer->drm_fmt->format == DRM_FORMAT_Y8 ||
> + layer->drm_fmt->format == DRM_FORMAT_Y10_P32) {
> + coeffs = csc_sdtv_to_rgb_yonly_matrix;
> + offsets = csc_sdtv_to_rgb_yonly_offsets;
> + } else if (layer->drm_fmt->is_yuv) {
> coeffs = csc_sdtv_to_rgb_matrix;
> offsets = csc_sdtv_to_rgb_offsets;
> } else {
>
This looks good. Feel free to add -
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Regards
Vishal Sagar