staging: iio: frequency: ad9832: Fix and

[PATCH v4 1/2] staging: iio: frequency: ad9832: Use SLEEP bit instead of RESET to disable output

Posted by Gabriel Shahrouzi 9 months, 2 weeks ago

According to the AD9832 datasheet (Table 10, D12 description), setting
the RESET bit forces the phase accumulator to zero, which corresponds to
a full-scale DC output, rather than disabling the output signal.

The correct way to disable the output and enter a low-power state is to
set the AD9832_SLEEP bit (Table 10, D13 description), which powers down
the internal DAC current sources and disables internal clocks.

Fixes: ea707584bac1 ("Staging: IIO: DDS: AD9832 / AD9835 driver")
Cc: stable@vger.kernel.org
Signed-off-by: Gabriel Shahrouzi <gshahrouzi@gmail.com>
---
v3 -> v4:
	- Rebase changes ontop of most recent changes.
v2 -> v3:
v1 -> v2:
---
 drivers/staging/iio/frequency/ad9832.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
index 49388da5a684a..2e555084ff98a 100644
--- a/drivers/staging/iio/frequency/ad9832.c
+++ b/drivers/staging/iio/frequency/ad9832.c
@@ -236,7 +236,7 @@ static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
 		if (val)
 			st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR);
 		else
-			st->ctrl_src |= FIELD_PREP(AD9832_RESET, 1);
+			st->ctrl_src |= FIELD_PREP(AD9832_SLEEP, 1);
 
 		st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
 						  st->ctrl_src);
-- 
2.43.0

Re: [PATCH v4 1/2] staging: iio: frequency: ad9832: Use SLEEP bit instead of RESET to disable output

Posted by Andy Shevchenko 9 months, 2 weeks ago

On Fri, Apr 25, 2025 at 1:34 AM Gabriel Shahrouzi <gshahrouzi@gmail.com> wrote:
>
> According to the AD9832 datasheet (Table 10, D12 description), setting
> the RESET bit forces the phase accumulator to zero, which corresponds to
> a full-scale DC output, rather than disabling the output signal.
>
> The correct way to disable the output and enter a low-power state is to
> set the AD9832_SLEEP bit (Table 10, D13 description), which powers down
> the internal DAC current sources and disables internal clocks.

...

>                 if (val)
>                         st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR);
>                 else
> -                       st->ctrl_src |= FIELD_PREP(AD9832_RESET, 1);
> +                       st->ctrl_src |= FIELD_PREP(AD9832_SLEEP, 1);

From the code perspective this allows combinations of the bits to be
set. So, what does the datasheet say about SLEEP+RESET, or RESET+CLR,
or other combinations of these 3 bits?

-- 
With Best Regards,
Andy Shevchenko

[PATCH v4 1/2] staging: iio: frequency: ad9832: Use SLEEP bit instead of RESET to disable output
[PATCH v4 2/2] staging: iio: frequency: ad9832: Refactor powerdown control