Add DT bindings for Microchip Azurite DPLL chip family. These chips
provide up to 5 independent DPLL channels, 10 differential or
single-ended inputs and 10 differential or 20 single-ended outputs.
They can be connected via I2C or SPI busses.
Check:
$ make dt_binding_check DT_SCHEMA_FILES=/dpll/
SCHEMA Documentation/devicetree/bindings/processed-schema.json
/home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition
CHKDT ./Documentation/devicetree/bindings
LINT ./Documentation/devicetree/bindings
DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb
DTEX Documentation/devicetree/bindings/dpll/microchip,zl30731.example.dts
DTC [C] Documentation/devicetree/bindings/dpll/microchip,zl30731.example.dtb
DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
---
v3->v4:
* fixed $Id
* dpll-pin type property renamed to connection type
v1->v3:
* single file for both i2c & spi
* 5 compatibles for all supported chips from the family
---
.../bindings/dpll/microchip,zl30731.yaml | 115 ++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
new file mode 100644
index 0000000000000..17747f754b845
--- /dev/null
+++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Azurite DPLL device
+
+maintainers:
+ - Ivan Vecera <ivecera@redhat.com>
+
+description:
+ Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
+ provides up to 5 independent DPLL channels, up to 10 differential or
+ single-ended inputs and 10 differential or 20 single-ended outputs.
+ These devices support both I2C and SPI interfaces.
+
+properties:
+ compatible:
+ enum:
+ - microchip,zl30731
+ - microchip,zl30732
+ - microchip,zl30733
+ - microchip,zl30734
+ - microchip,zl30735
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/dpll/dpll-device.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll@70 {
+ compatible = "microchip,zl30732";
+ reg = <0x70>;
+ dpll-types = "pps", "eec";
+
+ input-pins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pin@0 { /* REF0P */
+ reg = <0>;
+ connection-type = "ext";
+ label = "Input 0";
+ supported-frequencies-hz = /bits/ 64 <1 1000>;
+ };
+ };
+
+ output-pins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pin@3 { /* OUT1N */
+ reg = <3>;
+ connection-type = "gnss";
+ esync-control;
+ label = "Output 1";
+ supported-frequencies-hz = /bits/ 64 <1 10000>;
+ };
+ };
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll@70 {
+ compatible = "microchip,zl30731";
+ reg = <0x70>;
+ spi-max-frequency = <12500000>;
+
+ dpll-types = "pps";
+
+ input-pins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pin@0 { /* REF0P */
+ reg = <0>;
+ connection-type = "ext";
+ label = "Input 0";
+ supported-frequencies-hz = /bits/ 64 <1 1000>;
+ };
+ };
+
+ output-pins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pin@3 { /* OUT1N */
+ reg = <3>;
+ connection-type = "gnss";
+ esync-control;
+ label = "Output 1";
+ supported-frequencies-hz = /bits/ 64 <1 10000>;
+ };
+ };
+ };
+ };
+...
--
2.49.0On Thu, Apr 24, 2025 at 05:47:16PM GMT, Ivan Vecera wrote: > Add DT bindings for Microchip Azurite DPLL chip family. These chips > provide up to 5 independent DPLL channels, 10 differential or > single-ended inputs and 10 differential or 20 single-ended outputs. > They can be connected via I2C or SPI busses. > > Check: > $ make dt_binding_check DT_SCHEMA_FILES=/dpll/ None of these commands belong to the commit msg. Look at all other commits: do you see it anywhere? > SCHEMA Documentation/devicetree/bindings/processed-schema.json > /home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition > CHKDT ./Documentation/devicetree/bindings > LINT ./Documentation/devicetree/bindings > DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb > DTEX Documentation/devicetree/bindings/dpll/microchip,zl30731.example.dts > DTC [C] Documentation/devicetree/bindings/dpll/microchip,zl30731.example.dtb > DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb > With above fixed: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- <form letter> This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions of patchset, under or above your Signed-off-by tag, unless patch changed significantly (e.g. new properties added to the DT bindings). Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577 </form letter> Best regards, Krzysztof
On 25. 04. 25 9:41 dop., Krzysztof Kozlowski wrote: > On Thu, Apr 24, 2025 at 05:47:16PM GMT, Ivan Vecera wrote: >> Add DT bindings for Microchip Azurite DPLL chip family. These chips >> provide up to 5 independent DPLL channels, 10 differential or >> single-ended inputs and 10 differential or 20 single-ended outputs. >> They can be connected via I2C or SPI busses. >> >> Check: >> $ make dt_binding_check DT_SCHEMA_FILES=/dpll/ > > None of these commands belong to the commit msg. Look at all other > commits: do you see it anywhere? +1 >> SCHEMA Documentation/devicetree/bindings/processed-schema.json >> /home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition >> CHKDT ./Documentation/devicetree/bindings >> LINT ./Documentation/devicetree/bindings >> DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb >> DTEX Documentation/devicetree/bindings/dpll/microchip,zl30731.example.dts >> DTC [C] Documentation/devicetree/bindings/dpll/microchip,zl30731.example.dtb >> DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb >> > > With above fixed: > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Thank you. I. > --- > > <form letter> > This is an automated instruction, just in case, because many review tags > are being ignored. If you know the process, you can skip it (please do > not feel offended by me posting it here - no bad intentions intended). > If you do not know the process, here is a short explanation: > > Please add Acked-by/Reviewed-by/Tested-by tags when posting new > versions of patchset, under or above your Signed-off-by tag, unless > patch changed significantly (e.g. new properties added to the DT > bindings). Tag is "received", when provided in a message replied to you > on the mailing list. Tools like b4 can help here. However, there's no > need to repost patches *only* to add the tags. The upstream maintainer > will do that for tags received on the version they apply. > > https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577 > </form letter> > > Best regards, > Krzysztof >
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