[v2] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

[PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

Posted by Rengarajan S 9 months, 2 weeks ago

Systems that issue PCIe hot reset requests during a suspend/resume
cycle cause PCI1XXXX device revisions prior to C0 to get its UART
configuration registers reset to hardware default values. This results
in device inaccessibility and data transfer failures. Starting with
Revision C0, support was added in the device hardware (via the Hot
Reset Disable Bit) to allow resetting only the PCIe interface and its
associated logic, but preserving the UART configuration during a hot
reset. This patch enables the hot reset disable feature during suspend/
resume for C0 and later revisions of the device.

v2
Retained the original writel and simplified the hot reset condition
v1
Initial Commit.

Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
---
 drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
index e9c51d4e447d..61849312393b 100644
--- a/drivers/tty/serial/8250/8250_pci1xxxx.c
+++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
@@ -115,6 +115,7 @@
 
 #define UART_RESET_REG				0x94
 #define UART_RESET_D3_RESET_DISABLE		BIT(16)
+#define UART_RESET_HOT_RESET_DISABLE            BIT(17)
 
 #define UART_BURST_STATUS_REG			0x9C
 #define UART_TX_BURST_FIFO			0xA0
@@ -620,6 +621,10 @@ static int pci1xxxx_suspend(struct device *dev)
 	}
 
 	data = readl(p + UART_RESET_REG);
+
+	if (priv->dev_rev >= 0xC0)
+		data |= UART_RESET_HOT_RESET_DISABLE;
+
 	writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
 
 	if (wakeup)
@@ -647,7 +652,12 @@ static int pci1xxxx_resume(struct device *dev)
 	}
 
 	data = readl(p + UART_RESET_REG);
+
+	if (priv->dev_rev >= 0xC0)
+		data &= ~UART_RESET_HOT_RESET_DISABLE;
+
 	writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
+
 	iounmap(p);
 
 	for (i = 0; i < priv->nr; i++) {
-- 
2.25.1

Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

Posted by Greg KH 9 months, 2 weeks ago

On Thu, Apr 24, 2025 at 09:29:13AM +0530, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> configuration registers reset to hardware default values. This results
> in device inaccessibility and data transfer failures. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the UART configuration during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
> 
> v2
> Retained the original writel and simplified the hot reset condition
> v1
> Initial Commit.
> 
> Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
> ---
>  drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
> index e9c51d4e447d..61849312393b 100644
> --- a/drivers/tty/serial/8250/8250_pci1xxxx.c
> +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
> @@ -115,6 +115,7 @@
>  
>  #define UART_RESET_REG				0x94
>  #define UART_RESET_D3_RESET_DISABLE		BIT(16)
> +#define UART_RESET_HOT_RESET_DISABLE            BIT(17)

You forgot to use tabs here :(

Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

Posted by Rengarajan.S@microchip.com 9 months, 2 weeks ago

Hi Greg,

Thanks for reviewing the patch.

On Fri, 2025-04-25 at 13:45 +0200, Greg KH wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Thu, Apr 24, 2025 at 09:29:13AM +0530, Rengarajan S wrote:
> > Systems that issue PCIe hot reset requests during a suspend/resume
> > cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> > configuration registers reset to hardware default values. This
> > results
> > in device inaccessibility and data transfer failures. Starting with
> > Revision C0, support was added in the device hardware (via the Hot
> > Reset Disable Bit) to allow resetting only the PCIe interface and
> > its
> > associated logic, but preserving the UART configuration during a
> > hot
> > reset. This patch enables the hot reset disable feature during
> > suspend/
> > resume for C0 and later revisions of the device.
> > 
> > v2
> > Retained the original writel and simplified the hot reset condition
> > v1
> > Initial Commit.
> > 
> > Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
> > ---
> >  drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c
> > b/drivers/tty/serial/8250/8250_pci1xxxx.c
> > index e9c51d4e447d..61849312393b 100644
> > --- a/drivers/tty/serial/8250/8250_pci1xxxx.c
> > +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
> > @@ -115,6 +115,7 @@
> > 
> >  #define UART_RESET_REG                               0x94
> >  #define UART_RESET_D3_RESET_DISABLE          BIT(16)
> > +#define UART_RESET_HOT_RESET_DISABLE            BIT(17)
> 
> You forgot to use tabs here :(

Apologies, will update in the next revision.

>

Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

Posted by Jiri Slaby 9 months, 2 weeks ago

On 24. 04. 25, 5:59, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> configuration registers reset to hardware default values. This results
> in device inaccessibility and data transfer failures. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the UART configuration during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
> 
> v2
> Retained the original writel and simplified the hot reset condition
> v1
> Initial Commit.

This should have been under the --- line below.

> Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>

Reviewed-by: Jiri Slaby <jirislaby@kernel.org>

> ---

vvvvv here

>   drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)

thanks,
-- 
js
suse labs

Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices

Posted by Rengarajan.S@microchip.com 9 months, 2 weeks ago

Hi Jiri,

Thanks for reviewing the patch.

On Thu, 2025-04-24 at 10:44 +0200, Jiri Slaby wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On 24. 04. 25, 5:59, Rengarajan S wrote:
> > Systems that issue PCIe hot reset requests during a suspend/resume
> > cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> > configuration registers reset to hardware default values. This
> > results
> > in device inaccessibility and data transfer failures. Starting with
> > Revision C0, support was added in the device hardware (via the Hot
> > Reset Disable Bit) to allow resetting only the PCIe interface and
> > its
> > associated logic, but preserving the UART configuration during a
> > hot
> > reset. This patch enables the hot reset disable feature during
> > suspend/
> > resume for C0 and later revisions of the device.
> > 
> > v2
> > Retained the original writel and simplified the hot reset condition
> > v1
> > Initial Commit.
> 
> This should have been under the --- line below.

Sure will update in the next revision.

> 
> > Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
> 
> Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
> 
> > ---
> 
> vvvvv here
> 
> >   drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> 
> thanks,
> --
> js
> suse labs