Register definitions were scattered with ambiguous names (e.g.,
PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked
hierarchical grouping. Magic values for bit operations reduced code
clarity.
Group registers and their associated bitfields logically. This improves
maintainability and aligns the code with hardware documentation.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++--------
1 file changed, 24 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index fd5827bbfae3..cdc8afc6cfc1 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -8,6 +8,7 @@
* Author: Simon Xue <xxm@rock-chips.com>
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/irqchip/chained_irq.h>
@@ -34,30 +35,35 @@
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
-#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
-#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
-#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
-#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
-#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04
+#define PCIE_CLIENT_GENERAL_CONTROL 0x0
+#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
+#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
+#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
+#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
+
+#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4
+#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
+
#define PCIE_CLIENT_INTR_STATUS_MISC 0x10
+#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
+#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
+
+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
#define PCIE_CLIENT_INTR_MASK_MISC 0x24
+
#define PCIE_CLIENT_POWER 0x2c
+#define PME_READY_ENTER_L23 BIT(3)
+
#define PCIE_CLIENT_MSG_GEN 0x34
-#define PME_READY_ENTER_L23 BIT(3)
-#define PME_TURN_OFF (BIT(4) | BIT(20))
-#define PME_TO_ACK (BIT(9) | BIT(25))
-#define PCIE_SMLH_LINKUP BIT(16)
-#define PCIE_RDLH_LINKUP BIT(17)
-#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
-#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
-#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
-#define PCIE_CLIENT_GENERAL_CONTROL 0x0
-#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
-#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
+#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4))
+#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9))
+
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
+
#define PCIE_CLIENT_LTSSM_STATUS 0x300
-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
-#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
+#define PCIE_LINKUP_MASK GENMASK(17, 16)
+#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
struct rockchip_pcie {
struct dw_pcie pci;
--
2.25.1On Tue, Apr 22, 2025 at 07:28:29PM +0800, Hans Zhang wrote: > Register definitions were scattered with ambiguous names (e.g., > PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked > hierarchical grouping. Magic values for bit operations reduced code > clarity. > > Group registers and their associated bitfields logically. This improves > maintainability and aligns the code with hardware documentation. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++-------- > 1 file changed, 24 insertions(+), 18 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index fd5827bbfae3..cdc8afc6cfc1 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -8,6 +8,7 @@ > * Author: Simon Xue <xxm@rock-chips.com> > */ > > +#include <linux/bitfield.h> > #include <linux/clk.h> > #include <linux/gpio/consumer.h> > #include <linux/irqchip/chained_irq.h> > @@ -34,30 +35,35 @@ > > #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) > > -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) > -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) > -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 > +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 > +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) > +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) > + > +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 > +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 > + > #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 > +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) > +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) > + > +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c > #define PCIE_CLIENT_INTR_MASK_MISC 0x24 > + > #define PCIE_CLIENT_POWER 0x2c > +#define PME_READY_ENTER_L23 BIT(3) > + > #define PCIE_CLIENT_MSG_GEN 0x34 > -#define PME_READY_ENTER_L23 BIT(3) > -#define PME_TURN_OFF (BIT(4) | BIT(20)) > -#define PME_TO_ACK (BIT(9) | BIT(25)) > -#define PCIE_SMLH_LINKUP BIT(16) > -#define PCIE_RDLH_LINKUP BIT(17) > -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) This patch removes PCIE_LINKUP, without adding it somewhere else so I don't think this patch will compile. I think the removal of this line has to be in patch 3/3. Also, I think that Bjorn's primary concern: """ The #defines for register offsets and bits are kind of a mess, e.g., PCIE_SMLH_LINKUP, PCIE_RDLH_LINKUP, PCIE_LINKUP, PCIE_L0S_ENTRY, and PCIE_LTSSM_STATUS_MASK are in PCIE_CLIENT_LTSSM_STATUS, but you couldn't tell that from the names, and they're not even defined together. """" is that the fields are not prefixed with the register name. the secondary concern is that they are not grouped together. This patch is just solving the secondary concern. Since you are fixing his secondary concern, should you perhaps also address his primary concern? Kind regards, Niklas
On 2025/4/22 20:30, Niklas Cassel wrote: > On Tue, Apr 22, 2025 at 07:28:29PM +0800, Hans Zhang wrote: >> Register definitions were scattered with ambiguous names (e.g., >> PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked >> hierarchical grouping. Magic values for bit operations reduced code >> clarity. >> >> Group registers and their associated bitfields logically. This improves >> maintainability and aligns the code with hardware documentation. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++-------- >> 1 file changed, 24 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> index fd5827bbfae3..cdc8afc6cfc1 100644 >> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> @@ -8,6 +8,7 @@ >> * Author: Simon Xue <xxm@rock-chips.com> >> */ >> >> +#include <linux/bitfield.h> >> #include <linux/clk.h> >> #include <linux/gpio/consumer.h> >> #include <linux/irqchip/chained_irq.h> >> @@ -34,30 +35,35 @@ >> >> #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) >> >> -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 >> +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 >> +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> + >> +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 >> +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 >> + >> #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 >> +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) >> +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) >> + >> +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c >> #define PCIE_CLIENT_INTR_MASK_MISC 0x24 >> + >> #define PCIE_CLIENT_POWER 0x2c >> +#define PME_READY_ENTER_L23 BIT(3) >> + >> #define PCIE_CLIENT_MSG_GEN 0x34 >> -#define PME_READY_ENTER_L23 BIT(3) >> -#define PME_TURN_OFF (BIT(4) | BIT(20)) >> -#define PME_TO_ACK (BIT(9) | BIT(25)) >> -#define PCIE_SMLH_LINKUP BIT(16) >> -#define PCIE_RDLH_LINKUP BIT(17) >> -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) > > This patch removes PCIE_LINKUP, without adding it somewhere else > so I don't think this patch will compile. > > I think the removal of this line has to be in patch 3/3. > > > > Also, I think that Bjorn's primary concern: > """ > The #defines for register offsets and bits are kind of a mess, > e.g., PCIE_SMLH_LINKUP, PCIE_RDLH_LINKUP, PCIE_LINKUP, > PCIE_L0S_ENTRY, and PCIE_LTSSM_STATUS_MASK are in > PCIE_CLIENT_LTSSM_STATUS, but you couldn't tell that from the > names, and they're not even defined together. > """" > > is that the fields are not prefixed with the register name. Hi Niklas, As per rk3588 TRM, section "11.4.2.1 PCIE_CLIENT Registers Summary Detail Registers Description" The register names are as follows. I plan to add comments for each register in the next version, and the comments come from the register description of TRM. /* General Control Register */ #define PCIE_CLIENT_GENERAL_CON 0x0 #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) /* Interrupt Status Register Related to Message Reception */ #define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 /* Interrupt Status Register Related to Legacy Interrupt */ #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 /* Interrupt Status Register Related to Miscellaneous Operation */ #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 #define PCIE_RDLH_LINK_UP_CHGED BIT(1) #define PCIE_LINK_REQ_RST_NOT_INT BIT(2) /* Interrupt Mask Register Related to Legacy Interrupt */ #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c /* Interrupt Mask Register Related to Miscellaneous Operation */ #define PCIE_CLIENT_INTR_MASK_MISC 0x24 /* Power Management Control Register */ #define PCIE_CLIENT_POWER_CON 0x2c #define PME_READY_ENTER_L23 BIT(3) /* Message Generation Control Register */ #define PCIE_CLIENT_MSG_GEN_CON 0x34 #define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4)) #define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9)) /* Hot Reset Control Register */ #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) /* LTSSM Status Register */ #define PCIE_CLIENT_LTSSM_STATUS 0x300 #define PCIE_SMLH_LINKUP BIT(16) #define PCIE_RDLH_LINKUP BIT(17) #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) Best regards, Hans > > the secondary concern is that they are not grouped together. > > This patch is just solving the secondary concern. > > Since you are fixing his secondary concern, should you perhaps also > address his primary concern? > > > > Kind regards, > Niklas
On 2025/4/22 20:30, Niklas Cassel wrote: > On Tue, Apr 22, 2025 at 07:28:29PM +0800, Hans Zhang wrote: >> Register definitions were scattered with ambiguous names (e.g., >> PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked >> hierarchical grouping. Magic values for bit operations reduced code >> clarity. >> >> Group registers and their associated bitfields logically. This improves >> maintainability and aligns the code with hardware documentation. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++-------- >> 1 file changed, 24 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> index fd5827bbfae3..cdc8afc6cfc1 100644 >> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> @@ -8,6 +8,7 @@ >> * Author: Simon Xue <xxm@rock-chips.com> >> */ >> >> +#include <linux/bitfield.h> >> #include <linux/clk.h> >> #include <linux/gpio/consumer.h> >> #include <linux/irqchip/chained_irq.h> >> @@ -34,30 +35,35 @@ >> >> #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) >> >> -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 >> +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 >> +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> + >> +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 >> +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 >> + >> #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 >> +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) >> +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) >> + >> +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c >> #define PCIE_CLIENT_INTR_MASK_MISC 0x24 >> + >> #define PCIE_CLIENT_POWER 0x2c >> +#define PME_READY_ENTER_L23 BIT(3) >> + >> #define PCIE_CLIENT_MSG_GEN 0x34 >> -#define PME_READY_ENTER_L23 BIT(3) >> -#define PME_TURN_OFF (BIT(4) | BIT(20)) >> -#define PME_TO_ACK (BIT(9) | BIT(25)) >> -#define PCIE_SMLH_LINKUP BIT(16) >> -#define PCIE_RDLH_LINKUP BIT(17) >> -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) > > This patch removes PCIE_LINKUP, without adding it somewhere else > so I don't think this patch will compile. > > I think the removal of this line has to be in patch 3/3. > Hi Niklas, Thank you very much for your reply. Yes, I replied to you in patch 0003. > > > Also, I think that Bjorn's primary concern: > """ > The #defines for register offsets and bits are kind of a mess, > e.g., PCIE_SMLH_LINKUP, PCIE_RDLH_LINKUP, PCIE_LINKUP, > PCIE_L0S_ENTRY, and PCIE_LTSSM_STATUS_MASK are in > PCIE_CLIENT_LTSSM_STATUS, but you couldn't tell that from the > names, and they're not even defined together. > """" > > is that the fields are not prefixed with the register name. > > the secondary concern is that they are not grouped together. > > This patch is just solving the secondary concern. > > Since you are fixing his secondary concern, should you perhaps also > address his primary concern? Ok. I missed this problem and I will fix it in the next version. Best regards, Hans
On Tue, Apr 22, 2025 at 07:28:29PM +0800, Hans Zhang wrote: > Register definitions were scattered with ambiguous names (e.g., > PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked > hierarchical grouping. Magic values for bit operations reduced code > clarity. > > Group registers and their associated bitfields logically. This improves > maintainability and aligns the code with hardware documentation. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++-------- > 1 file changed, 24 insertions(+), 18 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index fd5827bbfae3..cdc8afc6cfc1 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -8,6 +8,7 @@ > * Author: Simon Xue <xxm@rock-chips.com> > */ > > +#include <linux/bitfield.h> > #include <linux/clk.h> > #include <linux/gpio/consumer.h> > #include <linux/irqchip/chained_irq.h> > @@ -34,30 +35,35 @@ > > #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) > > -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) > -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) > -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 > +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 > +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) > +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) > + > +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 > +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 > + > #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 > +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) > +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) > + > +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c > #define PCIE_CLIENT_INTR_MASK_MISC 0x24 > + > #define PCIE_CLIENT_POWER 0x2c > +#define PME_READY_ENTER_L23 BIT(3) > + > #define PCIE_CLIENT_MSG_GEN 0x34 > -#define PME_READY_ENTER_L23 BIT(3) > -#define PME_TURN_OFF (BIT(4) | BIT(20)) > -#define PME_TO_ACK (BIT(9) | BIT(25)) > -#define PCIE_SMLH_LINKUP BIT(16) > -#define PCIE_RDLH_LINKUP BIT(17) > -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) > -#define PCIE_RDLH_LINK_UP_CHGED BIT(1) > -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) > -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 > -#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 > -#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c > +#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4)) > +#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9)) > + > #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 > +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) > + > #define PCIE_CLIENT_LTSSM_STATUS 0x300 > -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) > -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) > +#define PCIE_LINKUP_MASK GENMASK(17, 16) Here you are adding a macro (PCIE_LINKUP_MASK) that is not used. I suggest that you move the addition to the patch where it is actually used. Kind regards, Niklas
On 2025/4/22 19:47, Niklas Cassel wrote: > On Tue, Apr 22, 2025 at 07:28:29PM +0800, Hans Zhang wrote: >> Register definitions were scattered with ambiguous names (e.g., >> PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked >> hierarchical grouping. Magic values for bit operations reduced code >> clarity. >> >> Group registers and their associated bitfields logically. This improves >> maintainability and aligns the code with hardware documentation. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++-------- >> 1 file changed, 24 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> index fd5827bbfae3..cdc8afc6cfc1 100644 >> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> @@ -8,6 +8,7 @@ >> * Author: Simon Xue <xxm@rock-chips.com> >> */ >> >> +#include <linux/bitfield.h> >> #include <linux/clk.h> >> #include <linux/gpio/consumer.h> >> #include <linux/irqchip/chained_irq.h> >> @@ -34,30 +35,35 @@ >> >> #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) >> >> -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 >> +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 >> +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> + >> +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 >> +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 >> + >> #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 >> +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) >> +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) >> + >> +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c >> #define PCIE_CLIENT_INTR_MASK_MISC 0x24 >> + >> #define PCIE_CLIENT_POWER 0x2c >> +#define PME_READY_ENTER_L23 BIT(3) >> + >> #define PCIE_CLIENT_MSG_GEN 0x34 >> -#define PME_READY_ENTER_L23 BIT(3) >> -#define PME_TURN_OFF (BIT(4) | BIT(20)) >> -#define PME_TO_ACK (BIT(9) | BIT(25)) >> -#define PCIE_SMLH_LINKUP BIT(16) >> -#define PCIE_RDLH_LINKUP BIT(17) >> -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) >> -#define PCIE_RDLH_LINK_UP_CHGED BIT(1) >> -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) >> -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 >> -#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 >> -#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c >> +#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4)) >> +#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9)) >> + >> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 >> +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) >> + >> #define PCIE_CLIENT_LTSSM_STATUS 0x300 >> -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) >> -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) >> +#define PCIE_LINKUP_MASK GENMASK(17, 16) > > Here you are adding a macro (PCIE_LINKUP_MASK) that is not used. > > I suggest that you move the addition to the patch where it is actually used. > Hi Niklas, Thank you very much for your reply. Will change. Best regards, Hans
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