arm64: defconfig: Enable hwspinlock and eQEP for K3

[PATCH] arm64: defconfig: Enable hwspinlock and eQEP for K3

Posted by Judith Mendez 7 months, 3 weeks ago

Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices
across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by
default on am64x SK board.

Signed-off-by: Judith Mendez <jm@ti.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9e16b494ab0e2..1f7b97ff46a7e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1415,6 +1415,7 @@ CONFIG_CLK_GFM_LPASS_SM8250=m
 CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
 CONFIG_CLK_RENESAS_VBATTB=m
 CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_OMAP=m
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_TEGRA186_TIMER=y
 CONFIG_RENESAS_OSTM=y
@@ -1676,6 +1677,7 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
 CONFIG_INTERCONNECT_QCOM_SM8750=y
 CONFIG_INTERCONNECT_QCOM_X1E80100=y
 CONFIG_COUNTER=m
+CONFIG_TI_EQEP=m
 CONFIG_RZ_MTU3_CNT=m
 CONFIG_HTE=y
 CONFIG_HTE_TEGRA194=y
-- 
2.49.0

Re: [PATCH] arm64: defconfig: Enable hwspinlock and eQEP for K3

Posted by Nishanth Menon 7 months, 3 weeks ago

Hi Judith Mendez,

On Mon, 21 Apr 2025 15:10:55 -0500, Judith Mendez wrote:
> Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices
> across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by
> default on am64x SK board.
> 
> 

I have applied the following to branch ti-k3-config-next on [1].
Thank you!

[1/1] arm64: defconfig: Enable hwspinlock and eQEP for K3
      commit: 53802e60fbb57a6ddab01837a53e2040cd1f592a

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH] arm64: defconfig: Enable hwspinlock and eQEP for K3

Posted by Arnd Bergmann 7 months, 3 weeks ago

On Mon, Apr 21, 2025, at 22:10, Judith Mendez wrote:
> Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices
> across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by
> default on am64x SK board.
>
> Signed-off-by: Judith Mendez <jm@ti.com>

Acked-by: Arnd Bergmann <arnd@arndb.de>

The patch seems fine to me, but you should address it at the 
TI K3 maintainers, so they know they should apply it and forward
it to the SoC tree. You have Nishanth and Vignesh in Cc already,
so I assume they will pick it up from here, just put them in
'To' instead next time and move Catalin and Will to 'Cc' or
leave them off entirely.

> ---
>  arch/arm64/configs/defconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 9e16b494ab0e2..1f7b97ff46a7e 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1415,6 +1415,7 @@ CONFIG_CLK_GFM_LPASS_SM8250=m
>  CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
>  CONFIG_CLK_RENESAS_VBATTB=m
>  CONFIG_HWSPINLOCK=y
> +CONFIG_HWSPINLOCK_OMAP=m
>  CONFIG_HWSPINLOCK_QCOM=y
>  CONFIG_TEGRA186_TIMER=y
>  CONFIG_RENESAS_OSTM=y
> @@ -1676,6 +1677,7 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
>  CONFIG_INTERCONNECT_QCOM_SM8750=y
>  CONFIG_INTERCONNECT_QCOM_X1E80100=y
>  CONFIG_COUNTER=m
> +CONFIG_TI_EQEP=m
>  CONFIG_RZ_MTU3_CNT=m
>  CONFIG_HTE=y
>  CONFIG_HTE_TEGRA194=y
> -- 
> 2.49.0

Re: [PATCH] arm64: defconfig: Enable hwspinlock and eQEP for K3

Posted by Judith Mendez 7 months, 3 weeks ago

Hi Arnd,

On 4/22/25 1:37 AM, Arnd Bergmann wrote:
> On Mon, Apr 21, 2025, at 22:10, Judith Mendez wrote:
>> Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices
>> across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by
>> default on am64x SK board.
>>
>> Signed-off-by: Judith Mendez <jm@ti.com>
> 
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> 
> The patch seems fine to me, but you should address it at the
> TI K3 maintainers, so they know they should apply it and forward
> it to the SoC tree. You have Nishanth and Vignesh in Cc already,
> so I assume they will pick it up from here, just put them in
> 'To' instead next time and move Catalin and Will to 'Cc' or
> leave them off entirely.
> 

Will re-spin and fix the to and cc lists, thanks for reviewing!

~ Judith

>> ---
>>   arch/arm64/configs/defconfig | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index 9e16b494ab0e2..1f7b97ff46a7e 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -1415,6 +1415,7 @@ CONFIG_CLK_GFM_LPASS_SM8250=m
>>   CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
>>   CONFIG_CLK_RENESAS_VBATTB=m
>>   CONFIG_HWSPINLOCK=y
>> +CONFIG_HWSPINLOCK_OMAP=m
>>   CONFIG_HWSPINLOCK_QCOM=y
>>   CONFIG_TEGRA186_TIMER=y
>>   CONFIG_RENESAS_OSTM=y
>> @@ -1676,6 +1677,7 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
>>   CONFIG_INTERCONNECT_QCOM_SM8750=y
>>   CONFIG_INTERCONNECT_QCOM_X1E80100=y
>>   CONFIG_COUNTER=m
>> +CONFIG_TI_EQEP=m
>>   CONFIG_RZ_MTU3_CNT=m
>>   CONFIG_HTE=y
>>   CONFIG_HTE_TEGRA194=y
>> -- 
>> 2.49.0

Re: [PATCH] arm64: defconfig: Enable hwspinlock and eQEP for K3

Posted by Nishanth Menon 7 months, 3 weeks ago

On 09:15-20250422, Judith Mendez wrote:
> Hi Arnd,
> 
> On 4/22/25 1:37 AM, Arnd Bergmann wrote:
> > On Mon, Apr 21, 2025, at 22:10, Judith Mendez wrote:
> > > Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices
> > > across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by
> > > default on am64x SK board.
> > > 
> > > Signed-off-by: Judith Mendez <jm@ti.com>
> > 
> > Acked-by: Arnd Bergmann <arnd@arndb.de>
> > 
> > The patch seems fine to me, but you should address it at the
> > TI K3 maintainers, so they know they should apply it and forward
> > it to the SoC tree. You have Nishanth and Vignesh in Cc already,
> > so I assume they will pick it up from here, just put them in
> > 'To' instead next time and move Catalin and Will to 'Cc' or
> > leave them off entirely.
> > 
> 
> Will re-spin and fix the to and cc lists, thanks for reviewing!

There is no need to respin, it is already in my queue. Will pick it up
as part of usual process. The above information that Arnd provided is
for future reference.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH] arm64: defconfig: Enable hwspinlock and eQEP for K3

Posted by Judith Mendez 7 months, 3 weeks ago

Hi Nishanth,

On 4/22/25 9:22 AM, Nishanth Menon wrote:
> On 09:15-20250422, Judith Mendez wrote:
>> Hi Arnd,
>>
>> On 4/22/25 1:37 AM, Arnd Bergmann wrote:
>>> On Mon, Apr 21, 2025, at 22:10, Judith Mendez wrote:
>>>> Enable CONFIG_HWSPINLOCK_OMAP to allow usage of these devices
>>>> across K3 SoC's. Also enable CONFIG_TI_EQEP which is enabled by
>>>> default on am64x SK board.
>>>>
>>>> Signed-off-by: Judith Mendez <jm@ti.com>
>>>
>>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>>>
>>> The patch seems fine to me, but you should address it at the
>>> TI K3 maintainers, so they know they should apply it and forward
>>> it to the SoC tree. You have Nishanth and Vignesh in Cc already,
>>> so I assume they will pick it up from here, just put them in
>>> 'To' instead next time and move Catalin and Will to 'Cc' or
>>> leave them off entirely.
>>>
>>
>> Will re-spin and fix the to and cc lists, thanks for reviewing!
> 
> There is no need to respin, it is already in my queue. Will pick it up
> as part of usual process. The above information that Arnd provided is
> for future reference.
> 
Sounds good, thanks for the help.

~ Judith