[v1] riscv: Add vendor extensions support for SiFive

[PATCH 09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description

Posted by Cyan Yang 8 months ago

Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for
matrix multiply accumulate instructions support.

Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index be203df29eb8..ede6a58ccf53 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -681,6 +681,12 @@ properties:
             See more details in
             https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
 
+        - const: xsfvfwmaccqqq
+          description:
+            SiFive Matrix Multiply Accumulate Instruction Extensions Specification.
+            See more details in
+            https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction
+
         # T-HEAD
         - const: xtheadvector
           description:
-- 
2.39.5 (Apple Git-154)

Re: [PATCH 09/12] dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description

Posted by Conor Dooley 7 months, 3 weeks ago

On Fri, Apr 18, 2025 at 01:32:36PM +0800, Cyan Yang wrote:
> Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for
> matrix multiply accumulate instructions support.
> 
> Signed-off-by: Cyan Yang <cyan.yang@sifive.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>