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[PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528

Yao Zi posted 3 patches 8 months ago
[PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Posted by Yao Zi 8 months ago 
Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
I2C-4 and I2C-7 which come with only a set of possible pins, a default
pin configuration is included.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 826f9be0be19..2c9780069af9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -24,6 +24,14 @@ aliases {
 		gpio2 = &gpio2;
 		gpio3 = &gpio3;
 		gpio4 = &gpio4;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -465,6 +473,108 @@ uart7: serial@ffa28000 {
 			status = "disabled";
 		};
 
+		i2c0: i2c@ffa50000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa50000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@ffa58000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa58000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@ffa60000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa60000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2m1_xfer>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@ffa68000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa68000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@ffa70000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa70000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c4_xfer>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@ffa78000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa78000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@ffa80000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa80000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@ffa88000 {
+			compatible = "rockchip,rk3528-i2c",
+				     "rockchip,rk3399-i2c";
+			reg = <0x0 0xffa88000 0x0 0x1000>;
+			clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+			clock-names = "i2c", "pclk";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c7_xfer>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		saradc: adc@ffae0000 {
 			compatible = "rockchip,rk3528-saradc";
 			reg = <0x0 0xffae0000 0x0 0x10000>;
-- 
2.49.0
Re: [PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Posted by Jonas Karlman 7 months, 1 week ago 
On 2025-04-17 14:01, Yao Zi wrote:
> Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
> I2C-4 and I2C-7 which come with only a set of possible pins, a default
> pin configuration is included.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>

Reading from the i2c EEPROM on a E20C works with this, so this is:

Reviewed-by: Jonas Karlman <jonas@kwiboo.se>

Regards,
Jonas

> ---
>  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
>  1 file changed, 110 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index 826f9be0be19..2c9780069af9 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -24,6 +24,14 @@ aliases {
>  		gpio2 = &gpio2;
>  		gpio3 = &gpio3;
>  		gpio4 = &gpio4;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
>  		serial0 = &uart0;
>  		serial1 = &uart1;
>  		serial2 = &uart2;
> @@ -465,6 +473,108 @@ uart7: serial@ffa28000 {
>  			status = "disabled";
>  		};
>  
> +		i2c0: i2c@ffa50000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa50000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@ffa58000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa58000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@ffa60000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa60000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c2m1_xfer>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c@ffa68000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa68000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c4: i2c@ffa70000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa70000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c4_xfer>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c5: i2c@ffa78000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa78000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c6: i2c@ffa80000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa80000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2c7: i2c@ffa88000 {
> +			compatible = "rockchip,rk3528-i2c",
> +				     "rockchip,rk3399-i2c";
> +			reg = <0x0 0xffa88000 0x0 0x1000>;
> +			clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
> +			clock-names = "i2c", "pclk";
> +			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c7_xfer>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		saradc: adc@ffae0000 {
>  			compatible = "rockchip,rk3528-saradc";
>  			reg = <0x0 0xffae0000 0x0 0x10000>;
Re: [PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Posted by Krzysztof Kozlowski 8 months ago 
On 17/04/2025 14:01, Yao Zi wrote:
> Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
> I2C-4 and I2C-7 which come with only a set of possible pins, a default
> pin configuration is included.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
>  1 file changed, 110 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index 826f9be0be19..2c9780069af9 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -24,6 +24,14 @@ aliases {
>  		gpio2 = &gpio2;
>  		gpio3 = &gpio3;
>  		gpio4 = &gpio4;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
Aliases are not properties of the SoC but boards.

Best regards,
Krzysztof
Re: [PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Posted by Krzysztof Kozlowski 8 months ago 
On 17/04/2025 16:36, Krzysztof Kozlowski wrote:
> On 17/04/2025 14:01, Yao Zi wrote:
>> Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
>> I2C-4 and I2C-7 which come with only a set of possible pins, a default
>> pin configuration is included.
>>
>> Signed-off-by: Yao Zi <ziyao@disroot.org>
>> ---
>>  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
>>  1 file changed, 110 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
>> index 826f9be0be19..2c9780069af9 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
>> @@ -24,6 +24,14 @@ aliases {
>>  		gpio2 = &gpio2;
>>  		gpio3 = &gpio3;
>>  		gpio4 = &gpio4;
>> +		i2c0 = &i2c0;
>> +		i2c1 = &i2c1;
>> +		i2c2 = &i2c2;
>> +		i2c3 = &i2c3;
>> +		i2c4 = &i2c4;
>> +		i2c5 = &i2c5;
>> +		i2c6 = &i2c6;
>> +		i2c7 = &i2c7;
> Aliases are not properties of the SoC but boards.

Of course this should be: Bus/interface aliases are not...

Best regards,
Krzysztof
Re: [PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Posted by Yao Zi 8 months ago 
On Thu, Apr 17, 2025 at 04:36:57PM +0200, Krzysztof Kozlowski wrote:
> On 17/04/2025 16:36, Krzysztof Kozlowski wrote:
> > On 17/04/2025 14:01, Yao Zi wrote:
> >> Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
> >> I2C-4 and I2C-7 which come with only a set of possible pins, a default
> >> pin configuration is included.
> >>
> >> Signed-off-by: Yao Zi <ziyao@disroot.org>
> >> ---
> >>  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
> >>  1 file changed, 110 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> >> index 826f9be0be19..2c9780069af9 100644
> >> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> >> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> >> @@ -24,6 +24,14 @@ aliases {
> >>  		gpio2 = &gpio2;
> >>  		gpio3 = &gpio3;
> >>  		gpio4 = &gpio4;
> >> +		i2c0 = &i2c0;
> >> +		i2c1 = &i2c1;
> >> +		i2c2 = &i2c2;
> >> +		i2c3 = &i2c3;
> >> +		i2c4 = &i2c4;
> >> +		i2c5 = &i2c5;
> >> +		i2c6 = &i2c6;
> >> +		i2c7 = &i2c7;
> > Aliases are not properties of the SoC but boards.
> 
> Of course this should be: Bus/interface aliases are not...

Thanks for the explanation. Will move them to the board DT.

> Best regards,
> Krzysztof

Best regards,
Yao Zi
Re: [PATCH v2 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
Posted by Heiko Stübner 8 months ago 
Hi Krzysztof,

Am Donnerstag, 17. April 2025, 16:46:35 Mitteleuropäische Sommerzeit schrieb Yao Zi:
> On Thu, Apr 17, 2025 at 04:36:57PM +0200, Krzysztof Kozlowski wrote:
> > On 17/04/2025 16:36, Krzysztof Kozlowski wrote:
> > > On 17/04/2025 14:01, Yao Zi wrote:
> > >> Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
> > >> I2C-4 and I2C-7 which come with only a set of possible pins, a default
> > >> pin configuration is included.
> > >>
> > >> Signed-off-by: Yao Zi <ziyao@disroot.org>
> > >> ---
> > >>  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
> > >>  1 file changed, 110 insertions(+)
> > >>
> > >> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > >> index 826f9be0be19..2c9780069af9 100644
> > >> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > >> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > >> @@ -24,6 +24,14 @@ aliases {
> > >>  		gpio2 = &gpio2;
> > >>  		gpio3 = &gpio3;
> > >>  		gpio4 = &gpio4;
> > >> +		i2c0 = &i2c0;
> > >> +		i2c1 = &i2c1;
> > >> +		i2c2 = &i2c2;
> > >> +		i2c3 = &i2c3;
> > >> +		i2c4 = &i2c4;
> > >> +		i2c5 = &i2c5;
> > >> +		i2c6 = &i2c6;
> > >> +		i2c7 = &i2c7;
> > > Aliases are not properties of the SoC but boards.
> > 
> > Of course this should be: Bus/interface aliases are not...
> 
> Thanks for the explanation. Will move them to the board DT.

I think we're having that discussion for every soc :-) .

Uarts. gpios, i2c and spi are always labeled foo[0-...] in all pieces
of Rockchip documentation.

The i2c0 controller has pins i2c0-scl, i2c0_sda; i2c0-labeled iomem;
i2c0-labeled irq, clk_i2c0, resetn_i2c0.


I completely _agree_ that {sdhci, sdmmc, emmc, sdio} -> mmcX is fully
board specific, but i2c0 should always get the i2c0 label and no other
controller should occupy that soc-specific i2c0-space, because that would
cause confusion without end.


And with the above it makes no real sense repeating the same list for
every individual board.

If you _insist_ on this, then fine, but I really don't see the point.


Heiko

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