arch/x86/include/asm/intel-family.h | 2 ++ 1 file changed, 2 insertions(+)
Bartlett Lake has a P-core only product with Raptor Cove.
Signed-off-by: Pi Xiange <xiange.pi@intel.com>
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 3a97a7eefb51..405bde66032a 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -126,6 +126,8 @@
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
+#define INTEL_RAPTORCOVE IFM(6, 0xD7) /* Bartlett Lake */
+
/* "Hybrid" Processors (P-Core/E-Core) */
#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
--
2.31.1
* Pi Xiange <xiange.pi@intel.com> wrote: > Bartlett Lake has a P-core only product with Raptor Cove. > > Signed-off-by: Pi Xiange <xiange.pi@intel.com> > --- > arch/x86/include/asm/intel-family.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h > index 3a97a7eefb51..405bde66032a 100644 > --- a/arch/x86/include/asm/intel-family.h > +++ b/arch/x86/include/asm/intel-family.h > @@ -126,6 +126,8 @@ > #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */ > #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) BTW., does 0xAE have a model name too? Thanks, Ingo
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: d466304c4322ad391797437cd84cca7ce1660de0
Gitweb: https://git.kernel.org/tip/d466304c4322ad391797437cd84cca7ce1660de0
Author: Pi Xiange <xiange.pi@intel.com>
AuthorDate: Mon, 14 Apr 2025 11:28:39 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 16 Apr 2025 09:16:02 +02:00
x86/cpu: Add CPU model number for Bartlett Lake CPUs with Raptor Cove cores
Bartlett Lake has a P-core only product with Raptor Cove.
[ mingo: Switch around the define as pointed out by Christian Ludloff:
Ratpr Cove is the core, Bartlett Lake is the product.
Signed-off-by: Pi Xiange <xiange.pi@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Christian Ludloff <ludloff@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: "Ahmed S. Darwish" <darwi@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250414032839.5368-1-xiange.pi@intel.com
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 3a97a7e..be10c18 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -126,6 +126,8 @@
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
+#define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */
+
/* "Hybrid" Processors (P-Core/E-Core) */
#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 45842b59ec93a5c8f24b4e62f3a5759d3857c08e
Gitweb: https://git.kernel.org/tip/45842b59ec93a5c8f24b4e62f3a5759d3857c08e
Author: Pi Xiange <xiange.pi@intel.com>
AuthorDate: Mon, 14 Apr 2025 11:28:39 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Mon, 14 Apr 2025 17:19:30 +02:00
x86/cpu: Add CPU model number for Bartlett Lake CPUs with Raptor Cove cores
Bartlett Lake has a P-core only product with Raptor Cove.
[ mingo: Switch around the define as pointed out by Christian Ludloff:
Ratpr Cove is the core, Bartlett Lake is the product.
Signed-off-by: Pi Xiange <xiange.pi@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Christian Ludloff <ludloff@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: "Ahmed S. Darwish" <darwi@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250414032839.5368-1-xiange.pi@intel.com
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 3a97a7e..be10c18 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -126,6 +126,8 @@
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
+#define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */
+
/* "Hybrid" Processors (P-Core/E-Core) */
#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: f3b9b7278259477d03dc643058fd9de9369290cb
Gitweb: https://git.kernel.org/tip/f3b9b7278259477d03dc643058fd9de9369290cb
Author: Pi Xiange <xiange.pi@intel.com>
AuthorDate: Mon, 14 Apr 2025 11:28:39 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Mon, 14 Apr 2025 09:25:07 +02:00
x86/cpu: Add CPU model number for Bartlett Lake CPUs with Raptor Cove cores
Bartlett Lake has a P-core only product with Raptor Cove.
Signed-off-by: Pi Xiange <xiange.pi@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: "Ahmed S. Darwish" <darwi@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250414032839.5368-1-xiange.pi@intel.com
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 3a97a7e..405bde6 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -126,6 +126,8 @@
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
+#define INTEL_RAPTORCOVE IFM(6, 0xD7) /* Bartlett Lake */
+
/* "Hybrid" Processors (P-Core/E-Core) */
#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
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