[PATCH v4 0/3] QPIC v2 fixes for SDX75

Md Sadre Alam posted 3 patches 10 months ago
drivers/mtd/nand/qpic_common.c       |  8 ++++----
drivers/mtd/nand/raw/qcom_nandc.c    | 18 +++++++++++++++---
drivers/spi/spi-qpic-snand.c         |  1 +
include/linux/mtd/nand-qpic-common.h |  4 +---
4 files changed, 21 insertions(+), 10 deletions(-)
[PATCH v4 0/3] QPIC v2 fixes for SDX75
Posted by Md Sadre Alam 10 months ago
The BAM command descriptor provides only 18 bits to specify the NAND
register offset. Additionally, in the BAM command descriptor, the NAND
register offset is supposed to be specified as "(NANDc base - BAM base)
+ reg_off". Since, the BAM controller expecting the value in the form of
"NANDc base - BAM base", so that added a new field 'bam_offset' in the
NAND properties structure and use it while preparing the command descriptor.

Previously, the driver was specifying the NANDc base address in the BAM
command descriptor.

also fixing last codeword read in qcom_param_page_type_exec() and read
len for onfi param page.

v4:
 * updated commit message
 * Renamed nand_offset to bam_offset
 * Dropped this patch "spi: spi-qpic-snand: set nand_offset for ipq9574"
   as "Gabor" suggested at [1]
   [1]:https://lore.kernel.org/lkml/a72f0db0-fd49-4cff-bffe-671fc757a219@gmail.com/
 * Removed nandc_reg_phys(chip, offset) macro and implemented this in function
   itself
 * Merged "spi: spi-qpic-snand: set bam_offset for ipq9574" in 
   "mtd: rawnand: qcom: Pass 18 bit offset from QPIC base address to BAM"

v3:
 * Updated commit message
 * updated qpic_v2 to qpic_version2
 * Removed dev_cmd_reg_start = 0 in sdx55_nandc_props {}
 * Added new patch to add nand_offset in spi_qpic_snand
   driver

v2:
 * Updated commit message
 * Added stable kernel tag
 * Added Fixes tag
 * Renamed the variable from offset_from_qpic to nandc_offset
 * Set buf_count to 512 in the parameter page read
 * Replaced the buf_count value of 512 with the len in bytes 

v1:
 * These patches will fix the following:
 * 1) onfi param page read which was broken by exec_op() patch.
 * 2) Fixed offset passed to BAM from QPIC base


Md Sadre Alam (3):
  mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM base
  mtd: rawnand: qcom: Fix last codeword read in
    qcom_param_page_type_exec()
  mtd: rawnand: qcom: Fix read len for onfi param page

 drivers/mtd/nand/qpic_common.c       |  8 ++++----
 drivers/mtd/nand/raw/qcom_nandc.c    | 18 +++++++++++++++---
 drivers/spi/spi-qpic-snand.c         |  1 +
 include/linux/mtd/nand-qpic-common.h |  4 +---
 4 files changed, 21 insertions(+), 10 deletions(-)

-- 
2.34.1
Re: [PATCH v4 0/3] QPIC v2 fixes for SDX75
Posted by Miquel Raynal 9 months, 2 weeks ago
On Thu, 10 Apr 2025 15:30:16 +0530, Md Sadre Alam wrote:
> The BAM command descriptor provides only 18 bits to specify the NAND
> register offset. Additionally, in the BAM command descriptor, the NAND
> register offset is supposed to be specified as "(NANDc base - BAM base)
> + reg_off". Since, the BAM controller expecting the value in the form of
> "NANDc base - BAM base", so that added a new field 'bam_offset' in the
> NAND properties structure and use it while preparing the command descriptor.
> 
> [...]

Applied to nand/next, thanks!

[1/3] mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM base
      commit: ee000969f28bf579d3772bf7c0ae8aff86586e20
[2/3] mtd: rawnand: qcom: Fix last codeword read in qcom_param_page_type_exec()
      commit: 47bddabbf69da50999ec68be92b58356c687e1d6
[3/3] mtd: rawnand: qcom: Fix read len for onfi param page
      commit: e6031b11544b44966ba020c867fe438bccd3bdfa

Patche(s) should be available on mtd/linux.git and will be
part of the next PR (provided that no robot complains by then).

Kind regards,
Miquèl