From: zhangyu <zhangyu550@huawei.com>

Because the kernel code cannot be started from el1
according to the booting.rst.
It is found that CPTR_EL2.FPEN is not configured.
After the configuration, the problem is solved.

Signed-off-by: zhangyu <zhangyu550@huawei.com>
Signed-off-by: zhangxiquan <zhangxiquan@hisilicon.com>
---
 Documentation/arch/arm64/booting.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index dee7b6de864f..ccefc42b51bc 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
   - If EL2 is present and the kernel is entered at EL1:

     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+    - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.

   For CPUs with the Scalable Vector Extension (FEAT_SVE) present:

--
2.45.1.windows.1

On Tue, Apr 08, 2025 at 11:13:09AM +0800, Xiquan Zhang wrote:
> From: zhangyu <zhangyu550@huawei.com>
> 
> Because the kernel code cannot be started from el1
> according to the booting.rst.
> It is found that CPTR_EL2.FPEN is not configured.
> After the configuration, the problem is solved.
> 
> Signed-off-by: zhangyu <zhangyu550@huawei.com>
> Signed-off-by: zhangxiquan <zhangxiquan@hisilicon.com>
> ---
>  Documentation/arch/arm64/booting.rst | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
> index dee7b6de864f..ccefc42b51bc 100644
> --- a/Documentation/arch/arm64/booting.rst
> +++ b/Documentation/arch/arm64/booting.rst
> @@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
>    - If EL2 is present and the kernel is entered at EL1:
> 
>      - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
> +    - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.

Sorry, but I don't quite understand this. CPTR_EL2 has a different format
depending on HCR_EL2.E2H and the FPEN field only exists when that bit is
set to 1. In that case, however, why would the kernel be entered at EL1?

Will