The current device tree binding for the Andes AX45MP L2 cache enforces
a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
the QiLai SoC. This change allows both 1024 and 2048 as valid values for
"cache-sets".

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index d2cbe49f4e15..798aa71dc4ec 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -44,7 +44,7 @@ properties:
     const: 2
 
   cache-sets:
-    const: 1024
+    enum: [1024, 2048]
 
   cache-size:
     enum: [131072, 262144, 524288, 1048576, 2097152]
-- 
2.34.1

On Mon, 07 Apr 2025 18:49:34 +0800, Ben Zong-You Xie wrote:
> The current device tree binding for the Andes AX45MP L2 cache enforces
> a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
> the QiLai SoC. This change allows both 1024 and 2048 as valid values for
> "cache-sets".
> 
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
>  .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml       | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>