Document 'aux' clock which are used to supply the PCIe bus. This
is useful in case of a hardware setup, where the PCIe controller
input clock and the PCIe bus clock are supplied from the same
clock synthesiser, but from different differential clock outputs:
____________ _____________
| R-Car PCIe | | PCIe device |
| | | |
| PCIe RX<|==================|>PCIe TX |
| PCIe TX<|==================|>PCIe RX |
| | | |
| PCIe CLK<|======.. ..======|>PCIe CLK |
'------------' || || '-------------'
|| ||
____________ || ||
| 9FGV0441 | || ||
| | || ||
| CLK DIF0<|======'' ||
| CLK DIF1<|==========''
| CLK DIF2<|
| CLK DIF3<|
'------------'
The clock are named 'aux' because those are one of the clock listed in
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which
fit closest to the PCIe bus clock. According to that binding document,
the 'aux' clock describe clock which supply the PMC domain, which is
likely PCIe Mezzanine Card domain.
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
instead and add 'bus' clock outright ?
---
Cc: "Krzysztof Wilczyński" <kw@linux.com>
Cc: "Rafał Miłecki" <rafal@milecki.pl>
Cc: Aradhya Bhatia <a-bhatia1@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Junhao Xie <bigfoot@classfun.cn>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
V2: - Add TB from Niklas
- Document minItems in clock-names
---
.../devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
index bb3f843c59d91..528b916fdb99b 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -46,12 +46,15 @@ properties:
- const: app
clocks:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
clock-names:
+ minItems: 2
items:
- const: core
- const: ref
+ - const: aux
power-domains:
maxItems: 1
@@ -105,8 +108,8 @@ examples:
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "dma", "sft_ce", "app";
- clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
- clock-names = "core", "ref";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>, <&pcie0_clkgen>;
+ clock-names = "core", "ref", "aux";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 624>;
reset-names = "pwr";
--
2.47.2
On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: > Document 'aux' clock which are used to supply the PCIe bus. This > is useful in case of a hardware setup, where the PCIe controller > input clock and the PCIe bus clock are supplied from the same > clock synthesiser, but from different differential clock outputs: How different is this clock from the 'reference clock'? I'm not sure what you mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock and the binding already has 'ref' clock for that purpose. So I don't understand how this new clock is connected to the endpoint device. - Mani > > ____________ _____________ > | R-Car PCIe | | PCIe device | > | | | | > | PCIe RX<|==================|>PCIe TX | > | PCIe TX<|==================|>PCIe RX | > | | | | > | PCIe CLK<|======.. ..======|>PCIe CLK | > '------------' || || '-------------' > || || > ____________ || || > | 9FGV0441 | || || > | | || || > | CLK DIF0<|======'' || > | CLK DIF1<|=========='' > | CLK DIF2<| > | CLK DIF3<| > '------------' > > The clock are named 'aux' because those are one of the clock listed in > Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which > fit closest to the PCIe bus clock. According to that binding document, > the 'aux' clock describe clock which supply the PMC domain, which is > likely PCIe Mezzanine Card domain. > > Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> > --- > NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > instead and add 'bus' clock outright ? > --- > Cc: "Krzysztof Wilczyński" <kw@linux.com> > Cc: "Rafał Miłecki" <rafal@milecki.pl> > Cc: Aradhya Bhatia <a-bhatia1@ti.com> > Cc: Bjorn Helgaas <bhelgaas@google.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Junhao Xie <bigfoot@classfun.cn> > Cc: Kever Yang <kever.yang@rock-chips.com> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> > Cc: Magnus Damm <magnus.damm@gmail.com> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Cc: Neil Armstrong <neil.armstrong@linaro.org> > Cc: Rob Herring <robh@kernel.org> > Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-pci@vger.kernel.org > Cc: linux-renesas-soc@vger.kernel.org > --- > V2: - Add TB from Niklas > - Document minItems in clock-names > --- > .../devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > index bb3f843c59d91..528b916fdb99b 100644 > --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml > @@ -46,12 +46,15 @@ properties: > - const: app > > clocks: > - maxItems: 2 > + minItems: 2 > + maxItems: 3 > > clock-names: > + minItems: 2 > items: > - const: core > - const: ref > + - const: aux > > power-domains: > maxItems: 1 > @@ -105,8 +108,8 @@ examples: > <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "msi", "dma", "sft_ce", "app"; > - clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; > - clock-names = "core", "ref"; > + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>, <&pcie0_clkgen>; > + clock-names = "core", "ref", "aux"; > power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > resets = <&cpg 624>; > reset-names = "pwr"; > -- > 2.47.2 > -- மணிவண்ணன் சதாசிவம்
On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote: > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: >> Document 'aux' clock which are used to supply the PCIe bus. This >> is useful in case of a hardware setup, where the PCIe controller >> input clock and the PCIe bus clock are supplied from the same >> clock synthesiser, but from different differential clock outputs: > > How different is this clock from the 'reference clock'? I'm not sure what you > mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock > and the binding already has 'ref' clock for that purpose. So I don't understand > how this new clock is connected to the endpoint device. See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint) side. Both clock come from the same clock synthesizer, but from two separate clock outputs of the synthesizer. >> ____________ _____________ >> | R-Car PCIe | | PCIe device | >> | | | | >> | PCIe RX<|==================|>PCIe TX | >> | PCIe TX<|==================|>PCIe RX | >> | | | | >> | PCIe CLK<|======.. ..======|>PCIe CLK | >> '------------' || || '-------------' >> || || >> ____________ || || >> | 9FGV0441 | || || >> | | || || >> | CLK DIF0<|======'' || >> | CLK DIF1<|=========='' >> | CLK DIF2<| >> | CLK DIF3<| >> '------------'
On Mon, May 12, 2025 at 10:42:20PM +0200, Marek Vasut wrote:
> On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
> > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> > > Document 'aux' clock which are used to supply the PCIe bus. This
> > > is useful in case of a hardware setup, where the PCIe controller
> > > input clock and the PCIe bus clock are supplied from the same
> > > clock synthesiser, but from different differential clock outputs:
> >
> > How different is this clock from the 'reference clock'? I'm not sure what you
> > mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
> > and the binding already has 'ref' clock for that purpose. So I don't understand
> > how this new clock is connected to the endpoint device.
>
> See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller
> side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint)
> side. Both clock come from the same clock synthesizer, but from two separate
> clock outputs of the synthesizer.
>
Okay. So separate refclks are suppplied to the host and endpoint here and no,
you should not call the other one as 'aux' clock, it is still the refclk. In
this case, you should describe the endpoint refclk in the PCIe bridge node:
pcie@... {
clock = <refclk_host>;
...
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
clock = <refclk_ep>;
...
};
};
and use the pwrctrl driver PCI_PWRCTRL_SLOT to enable it. Right now, the slot
pwrctrl driver is not handling the refclk, but I can submit a patch for that.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 5/15/25 1:57 PM, Manivannan Sadhasivam wrote:
> On Mon, May 12, 2025 at 10:42:20PM +0200, Marek Vasut wrote:
>> On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
>>> On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
>>>> Document 'aux' clock which are used to supply the PCIe bus. This
>>>> is useful in case of a hardware setup, where the PCIe controller
>>>> input clock and the PCIe bus clock are supplied from the same
>>>> clock synthesiser, but from different differential clock outputs:
>>>
>>> How different is this clock from the 'reference clock'? I'm not sure what you
>>> mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
>>> and the binding already has 'ref' clock for that purpose. So I don't understand
>>> how this new clock is connected to the endpoint device.
>>
>> See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller
>> side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint)
>> side. Both clock come from the same clock synthesizer, but from two separate
>> clock outputs of the synthesizer.
>>
>
> Okay. So separate refclks are suppplied to the host and endpoint here and no,
> you should not call the other one as 'aux' clock, it is still the refclk. In
> this case, you should describe the endpoint refclk in the PCIe bridge node:
>
> pcie@... {
> clock = <refclk_host>;
> ...
>
> pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> clock = <refclk_ep>;
> ...
> };
> };
>
>
> and use the pwrctrl driver PCI_PWRCTRL_SLOT to enable it. Right now, the slot
> pwrctrl driver is not handling the refclk, but I can submit a patch for that.
I posted a new series now, you are on CC, see
[PATCH 1/2] PCI/pwrctrl: Add optional slot clock to pwrctrl driver for
PCI slots
Thanks
On Thu, May 15, 2025 at 6:57 AM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Mon, May 12, 2025 at 10:42:20PM +0200, Marek Vasut wrote:
> > On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
> > > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> > > > Document 'aux' clock which are used to supply the PCIe bus. This
> > > > is useful in case of a hardware setup, where the PCIe controller
> > > > input clock and the PCIe bus clock are supplied from the same
> > > > clock synthesiser, but from different differential clock outputs:
> > >
> > > How different is this clock from the 'reference clock'? I'm not sure what you
> > > mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
> > > and the binding already has 'ref' clock for that purpose. So I don't understand
> > > how this new clock is connected to the endpoint device.
> >
> > See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller
> > side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint)
> > side. Both clock come from the same clock synthesizer, but from two separate
> > clock outputs of the synthesizer.
> >
>
> Okay. So separate refclks are suppplied to the host and endpoint here and no,
> you should not call the other one as 'aux' clock, it is still the refclk. In
> this case, you should describe the endpoint refclk in the PCIe bridge node:
>
> pcie@... {
> clock = <refclk_host>;
> ...
>
> pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> clock = <refclk_ep>;
> ...
> };
> };
>
>
> and use the pwrctrl driver PCI_PWRCTRL_SLOT to enable it. Right now, the slot
> pwrctrl driver is not handling the refclk, but I can submit a patch for that.
There's another discussion about PCIe clocks here[1]. Seems there's a
variety of options here with spread-spectrum layered on top.
Rob
[1] https://lore.kernel.org/all/20250425092012.95418-2-cassel@kernel.org
On Mon, May 19, 2025 at 10:04:09AM -0500, Rob Herring wrote:
> On Thu, May 15, 2025 at 6:57 AM Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Mon, May 12, 2025 at 10:42:20PM +0200, Marek Vasut wrote:
> > > On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
> > > > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> > > > > Document 'aux' clock which are used to supply the PCIe bus. This
> > > > > is useful in case of a hardware setup, where the PCIe controller
> > > > > input clock and the PCIe bus clock are supplied from the same
> > > > > clock synthesiser, but from different differential clock outputs:
> > > >
> > > > How different is this clock from the 'reference clock'? I'm not sure what you
> > > > mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
> > > > and the binding already has 'ref' clock for that purpose. So I don't understand
> > > > how this new clock is connected to the endpoint device.
> > >
> > > See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the controller
> > > side, CLK_DIF1 is the bus (or 'aux') clock which feeds the bus (or endpoint)
> > > side. Both clock come from the same clock synthesizer, but from two separate
> > > clock outputs of the synthesizer.
> > >
> >
> > Okay. So separate refclks are suppplied to the host and endpoint here and no,
> > you should not call the other one as 'aux' clock, it is still the refclk. In
> > this case, you should describe the endpoint refclk in the PCIe bridge node:
> >
> > pcie@... {
> > clock = <refclk_host>;
> > ...
> >
> > pcie@0 {
> > device_type = "pci";
> > reg = <0x0 0x0 0x0 0x0 0x0>;
> > bus-range = <0x01 0xff>;
> > clock = <refclk_ep>;
> > ...
> > };
> > };
> >
> >
> > and use the pwrctrl driver PCI_PWRCTRL_SLOT to enable it. Right now, the slot
> > pwrctrl driver is not handling the refclk, but I can submit a patch for that.
>
> There's another discussion about PCIe clocks here[1]. Seems there's a
> variety of options here with spread-spectrum layered on top.
>
The other discussion is separate IMO. It just concerns how the endpoint detects
local clock vs supplied clock.
- Mani
--
மணிவண்ணன் சதாசிவம்
On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: > Document 'aux' clock which are used to supply the PCIe bus. This > is useful in case of a hardware setup, where the PCIe controller > input clock and the PCIe bus clock are supplied from the same > clock synthesiser, but from different differential clock outputs: > > ____________ _____________ > | R-Car PCIe | | PCIe device | > | | | | > | PCIe RX<|==================|>PCIe TX | > | PCIe TX<|==================|>PCIe RX | > | | | | > | PCIe CLK<|======.. ..======|>PCIe CLK | > '------------' || || '-------------' > || || > ____________ || || > | 9FGV0441 | || || > | | || || > | CLK DIF0<|======'' || > | CLK DIF1<|=========='' > | CLK DIF2<| > | CLK DIF3<| > '------------' > > The clock are named 'aux' because those are one of the clock listed in > Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which > fit closest to the PCIe bus clock. According to that binding document, > the 'aux' clock describe clock which supply the PMC domain, which is > likely PCIe Mezzanine Card domain. Pretty sure that PMC is "power management controller" given it talks about low power states. > > Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> > --- > NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml > instead and add 'bus' clock outright ? Based on the diagram, this has nothing to do with the specific controller. It should also probably a root port property, not host bridge. Rob
On 4/10/25 10:48 PM, Rob Herring wrote: > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: >> Document 'aux' clock which are used to supply the PCIe bus. This >> is useful in case of a hardware setup, where the PCIe controller >> input clock and the PCIe bus clock are supplied from the same >> clock synthesiser, but from different differential clock outputs: >> >> ____________ _____________ >> | R-Car PCIe | | PCIe device | >> | | | | >> | PCIe RX<|==================|>PCIe TX | >> | PCIe TX<|==================|>PCIe RX | >> | | | | >> | PCIe CLK<|======.. ..======|>PCIe CLK | >> '------------' || || '-------------' >> || || >> ____________ || || >> | 9FGV0441 | || || >> | | || || >> | CLK DIF0<|======'' || >> | CLK DIF1<|=========='' >> | CLK DIF2<| >> | CLK DIF3<| >> '------------' >> >> The clock are named 'aux' because those are one of the clock listed in >> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which >> fit closest to the PCIe bus clock. According to that binding document, >> the 'aux' clock describe clock which supply the PMC domain, which is >> likely PCIe Mezzanine Card domain. > > Pretty sure that PMC is "power management controller" given it talks > about low power states. > > >> >> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> >> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> >> --- >> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml >> instead and add 'bus' clock outright ? > > Based on the diagram, this has nothing to do with the specific > controller. It should also probably a root port property, not host > bridge. How would you suggest I describe the clock which supply the PCIe bus clock lane (CLK DIF1 in the diagram) , which have to be enabled together with clock which supply the PCIe controller input clock lane (CLK DIF0) ?
Hi Marek,
On Sun, 13 Apr 2025 at 11:29, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 4/10/25 10:48 PM, Rob Herring wrote:
> > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> >> Document 'aux' clock which are used to supply the PCIe bus. This
> >> is useful in case of a hardware setup, where the PCIe controller
> >> input clock and the PCIe bus clock are supplied from the same
> >> clock synthesiser, but from different differential clock outputs:
> >>
> >> ____________ _____________
> >> | R-Car PCIe | | PCIe device |
> >> | | | |
> >> | PCIe RX<|==================|>PCIe TX |
> >> | PCIe TX<|==================|>PCIe RX |
> >> | | | |
> >> | PCIe CLK<|======.. ..======|>PCIe CLK |
> >> '------------' || || '-------------'
> >> || ||
> >> ____________ || ||
> >> | 9FGV0441 | || ||
> >> | | || ||
> >> | CLK DIF0<|======'' ||
> >> | CLK DIF1<|==========''
> >> | CLK DIF2<|
> >> | CLK DIF3<|
> >> '------------'
> >>
> >> The clock are named 'aux' because those are one of the clock listed in
> >> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which
> >> fit closest to the PCIe bus clock. According to that binding document,
> >> the 'aux' clock describe clock which supply the PMC domain, which is
> >> likely PCIe Mezzanine Card domain.
> >
> > Pretty sure that PMC is "power management controller" given it talks
> > about low power states.
> >
> >
> >>
> >> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> >> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> >> ---
> >> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> >> instead and add 'bus' clock outright ?
> >
> > Based on the diagram, this has nothing to do with the specific
> > controller. It should also probably a root port property, not host
> > bridge.
> How would you suggest I describe the clock which supply the PCIe bus
> clock lane (CLK DIF1 in the diagram) , which have to be enabled together
> with clock which supply the PCIe controller input clock lane (CLK DIF0) ?
I think Rob wants you to add clocks/clock-names for this to
dtschema/schemas/pci/pci-bus-common.yaml. Then you can have pcie@M,N
subnode(s) with num-lanes, clock, and clock-names describing the PCIe
endpoint(s)?
git grep "pcie*@[0-9],[0-9]" -- $(git grep -l num-lanes -- Documentation/ )
Does that make sense?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 4/23/25 11:38 AM, Geert Uytterhoeven wrote: > Hi Marek, Hi, > On Sun, 13 Apr 2025 at 11:29, Marek Vasut <marek.vasut@mailbox.org> wrote: >> On 4/10/25 10:48 PM, Rob Herring wrote: >>> On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: >>>> Document 'aux' clock which are used to supply the PCIe bus. This >>>> is useful in case of a hardware setup, where the PCIe controller >>>> input clock and the PCIe bus clock are supplied from the same >>>> clock synthesiser, but from different differential clock outputs: >>>> >>>> ____________ _____________ >>>> | R-Car PCIe | | PCIe device | >>>> | | | | >>>> | PCIe RX<|==================|>PCIe TX | >>>> | PCIe TX<|==================|>PCIe RX | >>>> | | | | >>>> | PCIe CLK<|======.. ..======|>PCIe CLK | >>>> '------------' || || '-------------' >>>> || || >>>> ____________ || || >>>> | 9FGV0441 | || || >>>> | | || || >>>> | CLK DIF0<|======'' || >>>> | CLK DIF1<|=========='' >>>> | CLK DIF2<| >>>> | CLK DIF3<| >>>> '------------' >>>> >>>> The clock are named 'aux' because those are one of the clock listed in >>>> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which >>>> fit closest to the PCIe bus clock. According to that binding document, >>>> the 'aux' clock describe clock which supply the PMC domain, which is >>>> likely PCIe Mezzanine Card domain. >>> >>> Pretty sure that PMC is "power management controller" given it talks >>> about low power states. >>> >>> >>>> >>>> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> >>>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> >>>> --- >>>> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml >>>> instead and add 'bus' clock outright ? >>> >>> Based on the diagram, this has nothing to do with the specific >>> controller. It should also probably a root port property, not host >>> bridge. >> How would you suggest I describe the clock which supply the PCIe bus >> clock lane (CLK DIF1 in the diagram) , which have to be enabled together >> with clock which supply the PCIe controller input clock lane (CLK DIF0) ? > > I think Rob wants you to add clocks/clock-names for this to > dtschema/schemas/pci/pci-bus-common.yaml. Then you can have pcie@M,N > subnode(s) with num-lanes, clock, and clock-names describing the PCIe > endpoint(s)? > > git grep "pcie*@[0-9],[0-9]" -- $(git grep -l num-lanes -- Documentation/ ) > > Does that make sense? No, not really. There can be any arbitrary PCIe card plugged into the M.2 slot, so how can I predict what exactly will be plugged into the slot and describe it in DT up front this way ? -- Best regards, Marek Vasut
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