arm64: dts: qcom: sm8650: add the missing l2 cache node

[PATCH] arm64: dts: qcom: sm8650: add the missing l2 cache node

Posted by Pengyu Luo 10 months, 1 week ago

Only two little a520s share the same L2, every a720 has their own L2
cache.

Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index a2b3d97ab..f47f29ec8 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -187,7 +187,7 @@ cpu3: cpu@300 {
 			power-domain-names = "psci";
 
 			enable-method = "psci";
-			next-level-cache = <&l2_200>;
+			next-level-cache = <&l2_300>;
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 
@@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
 					 &epss_l3 SLAVE_EPSS_L3_SHARED>;
 
 			#cooling-cells = <2>;
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
 		};
 
 		cpu4: cpu@400 {
-- 
2.49.0

Re: [PATCH] arm64: dts: qcom: sm8650: add the missing l2 cache node

Posted by Bjorn Andersson 8 months, 4 weeks ago

On Sat, 05 Apr 2025 18:55:28 +0800, Pengyu Luo wrote:
> Only two little a520s share the same L2, every a720 has their own L2
> cache.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sm8650: add the missing l2 cache node
      commit: 4becd72352b6861de0c24074a8502ca85080fd63

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH] arm64: dts: qcom: sm8650: add the missing l2 cache node

Posted by Konrad Dybcio 10 months ago

On 4/5/25 12:55 PM, Pengyu Luo wrote:
> Only two little a520s share the same L2, every a720 has their own L2
> cache.
> 
> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH] arm64: dts: qcom: sm8650: add the missing l2 cache node

Posted by neil.armstrong@linaro.org 10 months ago

On 05/04/2025 12:55, Pengyu Luo wrote:
> Only two little a520s share the same L2, every a720 has their own L2
> cache.
> 
> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index a2b3d97ab..f47f29ec8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -187,7 +187,7 @@ cpu3: cpu@300 {
>   			power-domain-names = "psci";
>   
>   			enable-method = "psci";
> -			next-level-cache = <&l2_200>;
> +			next-level-cache = <&l2_300>;
>   			capacity-dmips-mhz = <1792>;
>   			dynamic-power-coefficient = <238>;
>   
> @@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
>   					 &epss_l3 SLAVE_EPSS_L3_SHARED>;
>   
>   			#cooling-cells = <2>;
> +
> +			l2_300: l2-cache {
> +				compatible = "cache";
> +				cache-level = <2>;
> +				cache-unified;
> +				next-level-cache = <&l3_0>;
> +			};
>   		};
>   
>   		cpu4: cpu@400 {

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>