A MediaTek DRAM controller interface to provide the current DDR
data rate.

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
 .../mediatek,mt8196-dramc.yaml                | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml
new file mode 100644
index 000000000000..c0b3e7166a87
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt8196-dramc.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2025 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt8196-dramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DRAM Controller (DRAMC)
+
+maintainers:
+  - Crystal Guo <crystal.guo@mediatek.com>
+
+description:
+  A MediaTek DRAM controller interface to provide the current data rate of DRAM.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8196-dramc
+
+  reg:
+    items:
+      - description: anaphy registers
+      - description: ddrphy registers
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        memory-controller@10236000 {
+            compatible = "mediatek,mt8196-dramc";
+            reg = <0 0x10236000 0 0x2000>,
+                  <0 0x10238000 0 0x2000>;
+        };
+    };
-- 
2.18.0

On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
> +maintainers:
> +  - Crystal Guo <crystal.guo@mediatek.com>
> +
> +description:
> +  A MediaTek DRAM controller interface to provide the current data rate of DRAM.

DRAM controller does not offer scaling? Or PHY/timing configuration?
This binding looks pretty incomplete.

> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8196-dramc
> +
> +  reg:
> +    items:
> +      - description: anaphy registers
> +      - description: ddrphy registers
> +
> +additionalProperties: false

If there is going to be any resend then this goes after required: block.

> +
> +required:
> +  - compatible
> +  - reg

Best regards,
Krzysztof

On Sun, 2025-04-06 at 14:35 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
> > +maintainers:
> > +  - Crystal Guo <crystal.guo@mediatek.com>
> > +
> > +description:
> > +  A MediaTek DRAM controller interface to provide the current data
> > rate of DRAM.
> 
> DRAM controller does not offer scaling? Or PHY/timing configuration?
> This binding looks pretty incomplete.
> 

The PHY/timing configuration is completed during the bootloader stage.
In the kernel, we currently only need to provide an interface to
retrieve the current DDR data rate.

> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8196-dramc
> > +
> > +  reg:
> > +    items:
> > +      - description: anaphy registers
> > +      - description: ddrphy registers
> > +
> > +additionalProperties: false
> 
> If there is going to be any resend then this goes after required:
> block.
> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> 
> Best regards,
> Krzysztof
> 

Okay, thanks for the suggestion.
I will adjust the order in the next version.

Best regards,
Crystal Guo

On 09/04/2025 09:16, Crystal Guo (郭晶) wrote:
> On Sun, 2025-04-06 at 14:35 +0200, Krzysztof Kozlowski wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
>>> +maintainers:
>>> +  - Crystal Guo <crystal.guo@mediatek.com>
>>> +
>>> +description:
>>> +  A MediaTek DRAM controller interface to provide the current data
>>> rate of DRAM.
>>
>> DRAM controller does not offer scaling? Or PHY/timing configuration?
>> This binding looks pretty incomplete.
>>
> 
> The PHY/timing configuration is completed during the bootloader stage.
> In the kernel, we currently only need to provide an interface to
> retrieve the current DDR data rate.
Not really, that's what you currently want to do in kernel, but not what
you for example will want next days. Binding is supposed to be complete,
so if you do not have any scaling/interconnect then extend the
description of hardware and explain that memory controller is non
configurable, cannot scale and it exposes only read interface. Or
something similar.

Best regards,
Krzysztof

On Wed, 2025-04-09 at 09:33 +0200, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 09/04/2025 09:16, Crystal Guo (郭晶) wrote:
> > On Sun, 2025-04-06 at 14:35 +0200, Krzysztof Kozlowski wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > On Thu, Apr 03, 2025 at 02:48:47PM GMT, Crystal Guo wrote:
> > > > +maintainers:
> > > > +  - Crystal Guo <crystal.guo@mediatek.com>
> > > > +
> > > > +description:
> > > > +  A MediaTek DRAM controller interface to provide the current
> > > > data
> > > > rate of DRAM.
> > > 
> > > DRAM controller does not offer scaling? Or PHY/timing
> > > configuration?
> > > This binding looks pretty incomplete.
> > > 
> > 
> > The PHY/timing configuration is completed during the bootloader
> > stage.
> > In the kernel, we currently only need to provide an interface to
> > retrieve the current DDR data rate.
> 
> Not really, that's what you currently want to do in kernel, but not
> what
> you for example will want next days. Binding is supposed to be
> complete,
> so if you do not have any scaling/interconnect then extend the
> description of hardware and explain that memory controller is non
> configurable, cannot scale and it exposes only read interface. Or
> something similar.
> 
> Best regards,
> Krzysztof

Okay, the following instructions will be added in the next version:
'A MediaTek DRAM controller interface that provides the current data
rate of DRAM.

This controller is designed solely to provide a read interface for
retrieving the DDR data rate. It does not support scaling or PHY/timing
configuration during the kernel stage, as these configurations are
already completed during the bootloader stage.'

Best regards,
Crystal Guo

Il 03/04/25 08:48, Crystal Guo ha scritto:
> A MediaTek DRAM controller interface to provide the current DDR
> data rate.
> 
> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>